Matrix Detector Line Addressing to Reduce Even/Odd Noise
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Solution Overview
Problem
Matrix detectors face significant parasitic noise due to parasitic capacitances caused by clock signals, which overwhelm the small signals from physical phenomena, especially in image sensors, making it difficult to distinguish between signals from odd and even rows.
Innovation Solution
A matrix detector design that includes a signal generator producing three clock signals, with a third clock signal applied to isolation circuits between stages and lines, allowing for synchronized selection and reduced parasitic noise through compensation capacitors and transistors, ensuring consistent signal levels across all rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two clock signals are used to drive alternating stages of the shift register, then the line addressing device can operate sequentially, but parasitic capacitances cause even/odd effect and noise that overwhelm detection signals
Solution Approach 1:
Isolation circuits are introduced as intermediary elements between the shift register stages and the pixel lines. These isolation circuits mediate the interaction between the clock signals and the pixel lines, preventing direct parasitic coupling while maintaining the sequential addressing function. The isolation circuits act as buffer stages that decouple the harmful parasitic effects from the detection path.
Solution Approach 2:
The harmful parasitic capacitance effects are extracted and isolated from the main detection path by separating the clock signal distribution function from the pixel line control function. The isolation circuits extract the clock signal timing function while removing the parasitic coupling to the pixel lines, allowing the detection signals to be read without contamination from clock-related noise.
2Device complexity
If clock signals are applied directly to shift register stages, then addressing control is simplified, but parasitic couplings generate noise that prevents accurate signal detection
Solution Approach 1:
The addressing control function is segmented into separate functional blocks: the shift register for token generation, isolation circuits for decoupling, and pixel line control for signal readout. This segmentation allows each block to perform its function independently, reducing parasitic interactions while maintaining overall control functionality. The isolation circuits specifically segment the clock signal path from the pixel line path.
Solution Approach 2:
Isolation circuits serve as intermediary stages between the shift register output and the pixel lines. These intermediaries maintain the addressing control functionality while preventing direct parasitic coupling. The isolation circuits translate the token signals from the shift register into controlled pixel line activation without allowing clock signal noise to couple into the detection path.
3Object-affected harmful factors
If isolation circuits with third clock signal are added, then parasitic noise is reduced, but device complexity increases
Solution Approach 1:
The third clock signal is designed to serve multiple functions simultaneously: it drives the isolation circuits to prevent parasitic coupling, it synchronizes the pixel line selection, and it maintains timing coherence across the matrix detector. This multi-functionality reduces the need for additional dedicated clock signals for each function, thereby limiting the increase in device complexity.
Solution Approach 2:
The isolation circuit functionality is merged with the existing shift register stage structure rather than being implemented as completely separate external circuits. The isolation circuits are integrated into the matrix detector architecture, sharing common substrates and signal routing where possible. This merging approach consolidates the increased complexity within a unified structure rather than adding separate independent systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the even/odd effect and parasitic noise, enabling accurate signal detection by maintaining consistent signal levels and minimizing parasitic couplings, thus enhancing the sensitivity of the matrix detector.
Implementation Method 1
parasitic capacitances caused by clock signals, which overwhelm the small signals from physical phenomena
Implementation Method 2
A matrix detector design that includes a signal generator producing three clock signals, with a third clock signal applied to isolation circuits between stages and lines, allowing for synchronized selection and reduced parasitic noise
Data Source
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AI summary
The invention relates to a matrix detector comprising: - a set of pixels arranged in a matrix according to lines (L) and columns, each pixel (P) being suitable for generating a signal depending on a physical phenomenon, - a signal generator (GSI) configured to generate two clock signals (CK1, CK 2) phase-shifted with respect to one another, - a device for addressing the lines comprising a shift register (SR), the shift register (SR) comprising a plurality of stages (ET) arranged in cascade, each stage (ET) being capable of receiving, alternately from one stage to another, a clock signal from the two clock signals (CK1, CK2), and being capable of issuing an intermediate output signal (OUTn), which can assume a high level (Von) and a low level (Voff), enabling activation and deactivation respectively of the pixels in the line, characterised in that the signal generator (GSI) is also configured to generate a third clock signal (CK3), the addressing device also comprising a plurality of isolation circuits (ISL), each isolation circuit (ISL) being connected between each stage (ET) and the corresponding line (LI) of the matrix, and configured to receive the third clock signal (CK3), the isolation circuit (ISL) being configured to issue a select signal (OUT_LINE_n) selecting the corresponding line of the matrix when the intermediate output signal (OUTn) and the third clock signal (CK3) are at a high level (Von).