Matrix Dimension Shuffling via Strided Memory Access

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Solution Overview

Problem

Existing matrix processing approaches are inefficient for complex operations like matrix multiplication and convolutions, particularly due to processor and memory latency, and are unable to perform matrix dimension shuffling with high efficiency, limiting their application in artificial intelligence and machine learning.

Innovation Solution

A matrix processing architecture that optimizes memory access through strided memory access and dimension shuffling using non-transpose and transpose convolutional reads, allowing for efficient execution of matrix operations and dimension reordering with minimal conversions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional matrix processing approaches are used, then general-purpose computing is maintained, but processing efficiency and memory access performance deteriorate due to processor and memory latency

Engineering Contradiction:
Improvematrix operation processing efficiencyVSAvoidprocessor and memory latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the matrix processing task into distinct phases: data loading phase and processing phase. By dividing the matrix data into blocks and processing them in stages, the system can overlap memory access operations with computation operations, thereby hiding memory latency and improving overall processing efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent loads matrix operand data into the matrix processing system before the actual processing begins. This preliminary data loading and positioning allows the processing units to immediately begin computation without waiting for memory access during processing, thus reducing processor and memory latency

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If complex matrix operations are performed with growing data sets, then application capabilities are improved, but processing performance is limited by memory and processor latency

Engineering Contradiction:
Improveapplication capability for AI and machine learningVSAvoidmatrix operation processing performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a specialized matrix processing dimension by implementing dedicated matrix processing units and memory structures optimized for matrix operations. This dimensional specialization allows the system to handle complex AI and machine learning workloads efficiently while maintaining high processing performance through architecture-specific optimizations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If matrix dimension shuffling is performed with existing methods, then data reordering is achieved, but processing efficiency deteriorates due to multiple conversion steps

Engineering Contradiction:
Improvedata reordering capabilityVSAvoiddimension shuffling efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent merges multiple dimension conversion operations into a single unified dimension shuffling operation. By combining what would traditionally require multiple separate transpose and reordering steps into one integrated operation, the system achieves data reordering with improved processing efficiency and reduced computational overhead

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3343355B1Dimension shuffling using matrix processors
Publication Date: 2022.08.31 INTEL CORP
  • EP3343355B1 patent drawingFigure 1
  • EP3343355B1 patent drawingFigure 2A
  • EP3343355B1 patent drawingFigure 2B~2C

AI summary

In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data associated with the input matrix may be accessed using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval. The data accessed using the one or more strided memory operations may be stored in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.