Matrix Device Driving Circuit Peak Current Reduction
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Solution Overview
Problem
Image display devices using line-sequential systems experience large instantaneous power consumption, leading to potential power cutoffs when using low-performance power supplies, such as button batteries, due to peak current flow in the data buffer circuit.
Innovation Solution
A driving circuit for matrix devices is designed with multistage operation units in the data latch circuits, allowing signal input to each data line per operation unit, reducing peak current and eliminating the need for a latch activation signal, thereby stabilizing operation even with low-performance power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the latch activation signal LAT is input and all latch circuits in the second data latch circuit operate all at once, then the image signals are output all at once to all data lines, but a large current is caused to instantaneously flow in the data buffer circuit, causing a voltage drop in the power supply
Solution Approach 1:
The data latch circuits are divided into multiple groups, where each group corresponds to a specific data line. Each group operates independently and simultaneously, allowing the image signals to be output to all data lines in parallel without causing a large instantaneous current surge. This segmentation of the latch circuits into multiple smaller operational units resolves the contradiction by maintaining fast signal input while distributing the power consumption across multiple smaller current flows instead of one large current flow.
2Productivity
If a large current is caused to instantaneously flow in the data buffer circuit, then the image signals are output all at once, but a voltage drop in the power supply occurs, causing power to be cut off one time and restored, thereby initializing the device
Solution Approach 1:
By dividing the data latch circuits into multiple groups that operate independently, the patent segments the large current flow into multiple smaller current flows. Each group outputs signals to its corresponding data line simultaneously, maintaining fast signal output speed, while the distributed current consumption prevents voltage drops that would cause power cutoffs and device initialization, thereby ensuring device stability.
Solution Approach 2:
Instead of activating all latch circuits simultaneously with a single latch activation signal (excessive action causing large current), the patent uses multiple groups of latch circuits that are activated in parallel but with distributed current draw (partial action). Each group operates at a lower current level, and the cumulative effect maintains signal output speed without exceeding the power supply's voltage stability threshold.
Data Source
AI summary
A driving circuit is provided which is applied to a matrix device having a plurality of functional elements arranged in a matrix, which is connected to the functional elements via data lines, and which has a plurality of blocks. The driving circuit includes a shift register which has a plurality of register sections, each of the register sections being corresponding to one of the plurality of blocks; a data signal line; a first data latch circuit connected to an output terminal of the shift register and the data signal line; and a second data latch circuit connected to the output terminal of the shift register and an output terminal of the first data latch circuit, and connected to the data line directly or via another circuit. The first and second data latch circuits are respectively divided into multistage operation units. Each of the operation units is corresponding to the one data line or the plurality of data lines and is corresponding to one of the plurality of blocks. An output terminal of the shift register belonging to a block B is connected to the operation unit of the first data latch circuit belonging to the block B, the output terminal of the shift register belonging to a block A is connected to the operation unit of the second data latch circuit belonging to the block B, and each of the block A and block B is one of the plurality of blocks.