Matrix Interleaver for SDRAM Throughput Optimization
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Solution Overview
Problem
Traditional data processing methods using Synchronous Dynamic Random Access Memory (SDRAM) result in wasted storage resources when the data to be transferred is not an integral multiple of 16 bits, leading to inefficient throughput and utilization.
Innovation Solution
A method and device that interleave and de-interleave data by combining columns of input data with the same delay time, writing them row-wise into off-chip memory, and then splitting them back into columns, optimizing data processing and memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional SDRAM buffering method is used, then data storage is simple, but storage resources are wasted when data bit width is not a multiple of 16 bits
Solution Approach 1:
The patent divides the data processing into multiple sub-interleavers, each handling a portion of the input data. By segmenting the data into columns and processing them through multiple sub-interleavers with different column widths, the system can efficiently handle various data bit widths without wasting SDRAM storage resources. Each sub-interleaver processes a specific column width, and the results are combined to produce the final interleaved output.
2Productivity
If data is buffered in SDRAM with fixed 16-bit width, then memory structure is simple, but throughput is reduced due to incomplete utilization
Solution Approach 1:
The patent merges multiple sub-interleavers to form a complete interleaver system. Each sub-interleaver processes a portion of the input data in parallel, and their outputs are combined to produce the final interleaved sequence. This merging approach increases throughput by utilizing the full 16-bit width of SDRAM effectively, while each individual sub-interleaver maintains a manageable structure.
Solution Approach 2:
The patent transforms the traditional single-column interleaving approach into a multi-column parallel processing structure. By organizing data into multiple columns and processing them simultaneously through different sub-interleavers, the system adds a dimensional aspect to the interleaving process, thereby increasing throughput without excessively complicating the overall structure.
3Productivity
If multiple sub-interleavers are used to improve throughput, then data processing efficiency increases, but system complexity increases
Solution Approach 1:
The patent applies local quality by making each sub-interleaver have a specific, optimized column width suited for its portion of the data. Instead of using identical structures for all sub-interleavers, each one is configured with appropriate local characteristics (different column widths) that match the specific processing requirements of its data segment, thereby improving overall throughput while keeping individual components relatively simple.
Data Source
AI summary
A method of interleaving comprising: generating a combined data by combining, a plurality of columns of input data to be inputted to a plurality of adjacent sub-interleavers into a column, wherein data within same rows among the plurality of columns of input data have same delay time; writing the combined data row by row into an off-chip memory; delaying the combined data, by the off-chip memory; and splitting data outputted by the off-chip memory into the plurality of columns such that each split column includes data corresponding to one of the plurality of adjacent sub-interleavers.