Matrix Memory Cell Array for Compact Image Display Substrate
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Solution Overview
Problem
Conventional liquid crystal displays face challenges in reducing the display substrate area around the display section while maintaining low power consumption and achieving high-definition image display, as the number of memory cells increases with the number of image data bits, leading to increased circuit width and difficulty in reducing pixel width.
Innovation Solution
The solution involves an image display apparatus with a display section where pixels are arrayed, an analogue image signal generation means, and an image signal storage means provided over the same insulating substrate, with memory cells disposed in a matrix fashion and selected by row-direction select metal interconnects, allowing digital image signals to be input/output via column-direction signal metal interconnects, enabling the generation and output of analogue signals using multiple select and signal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to store more image data bits, then the image data storage capacity is improved, but the circuit width and substrate area increase
Solution Approach 1:
The patent transitions from linear arrangement of memory cells to a two-dimensional matrix arrangement, allowing memory cells to be accessed via row and column select lines. This dimensional change enables much higher storage density on the same substrate area, resolving the contradiction between storage capacity and substrate area.
Solution Approach 2:
The memory cell array is segmented into multiple rows and columns, with independent select lines for each dimension. This segmentation allows parallel access to multiple memory cells simultaneously, increasing storage capacity without proportionally increasing the control circuit complexity or substrate area.
2Manufacturing precision
If the number of memory cells is increased to achieve high-definition display, then the image quality is improved, but the pixel width and circuit complexity increase
Solution Approach 1:
By organizing memory cells in a matrix with row and column select lines, the patent reduces the number of individual control lines needed compared to a linear arrangement. This dimensional organization enables high-definition display with manageable circuit complexity, as the matrix structure efficiently scales with increasing pixel counts.
3Productivity
If multiple memory gate lines are driven concurrently to increase data output speed, then the productivity is improved, but the power consumption increases
Solution Approach 1:
The patent employs periodic scanning of memory gate lines to sequentially access and output data from multiple memory cells. This periodic action allows concurrent driving of multiple gate lines in a time-multiplexed manner, achieving high data output speed while managing power consumption through controlled activation periods rather than continuous operation.
Data Source
AI summary
An image display apparatus with a portion of a display substrate area, around a display section, being small, low in power consumption, and capable of effecting high-definition image display. A built-in memory configuration is provided wherein one unit of analogue image signal is generated on the basis of a memory cell signal selected by not less than two lengths of select metal interconnects form a select circuit, and outputted by not less than two lengths of signal metal interconnects. Memory cells of a built-in memory are disposed in staggered arrangement. Respective pixels of a display section include a pixel switch and a capacitor, and a gate of the pixel switch is connected to a vertical scanning circuit via a gate line.