Matrix Multiplication Accelerator with Parallel Operation Units
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Solution Overview
Problem
Current methods for multiplying two N*N matrices are time-consuming, requiring N^3 operations in both vector processor and systolic array approaches, necessitating a more efficient solution to reduce computation time.
Innovation Solution
An operation accelerator is designed with a matrix multiplying circuit and adder circuit, comprising M operation groups with K operation blocks, each containing N operation units, allowing M*N*K multiplication operations within one clock cycle by performing parallel data processing and addition of results across operation blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a vector processor is used to calculate matrix multiplication, then the calculation can be performed with simple hardware structure, but the calculation time is long requiring N^3/M clock cycles
Solution Approach 1:
The patent segments the matrix multiplication operation into multiple parallel computation paths. The computation array is divided into multiple processing elements that can simultaneously perform multiplication and accumulation operations on different elements of the result matrix, thereby reducing the overall calculation time while maintaining hardware efficiency
Solution Approach 2:
The patent transitions from one-dimensional vector processing to two-dimensional matrix processing by organizing computation units in a grid structure. This allows simultaneous processing of multiple rows and columns, effectively adding a spatial dimension to the computation and achieving parallel speedup without proportionally increasing hardware complexity
2Loss of time
If a systolic array is used to increase calculation speed, then the calculation time is reduced to N clock cycles, but the device complexity increases with N^2 operation units
Solution Approach 1:
The patent designs computation units that can perform multiple functions - each unit can perform both multiplication and accumulation operations, and can process different data elements at different time steps. This multi-functionality reduces the total number of dedicated operation units needed compared to a traditional systolic array
Solution Approach 2:
The patent introduces dynamic data flow control and reconfigurable computation paths that allow the same hardware structure to adapt to different matrix sizes and operation requirements. This dynamic behavior enables the system to maintain high computational efficiency without requiring a fixed large-scale systolic array structure
Data Source
AI summary
The present invention in the field of data calculation technologies, discloses an operation accelerator, to reduce time for performing a multiplication operation on two N*N matrices. The operation accelerator includes: a first memory, a second memory, an operation circuit, and a controller. The operation circuit performs data communication with the first memory and the second memory by using a bus. The operation circuit is configured to: extract matrix data from the first memory and the second memory, and perform a multiplication operation. The controller is configured to control, according to a preset program or instruction, the operation circuit to complete the multiplication operation. The operation accelerator is configured to perform a multiplication operation on two matrices.