Matrix Multiplication Processor Architecture with Wallace Tree Multipliers
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Solution Overview
Problem
Existing dedicated processors for matrix multiplication in deep learning algorithms face limitations in universality and computing performance due to restricted parallelism, especially when dealing with matrices having a small number of rows or columns, leading to inefficient resource utilization and reduced processing speed.
Innovation Solution
A processor architecture with an array processor comprising multiple processing units and on-chip memory units, where 1×n row vectors from the multiplicand matrix and n×k submatrices from the multiplier matrix are read and processed in parallel, utilizing Wallace tree multipliers to execute vector multiplication operations, thereby avoiding parallelism in the M dimension and enhancing parallelism in the K and N dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallelism is mined in the M dimension, then computing performance is improved, but architecture universality deteriorates when dealing with matrices having a small number of rows
Solution Approach 1:
The patent segments the matrix multiplication operation into two independent parallelism mining dimensions: K dimension (column vectors of multiplier matrix) and N dimension (row vectors of multiplicand matrix). Each dimension can be processed independently through separate processing units, allowing flexible adaptation to different matrix sizes without requiring parallelism in both dimensions simultaneously, thus maintaining universality while improving computing performance.
Solution Approach 2:
The patent introduces a new dimension of parallelism by simultaneously exploiting both K dimension and N dimension parallelism in the array processor. Instead of choosing one dimension, the system creates a two-dimensional parallelism structure where processing units can operate independently in both dimensions, achieving higher computing performance while maintaining architectural flexibility for various matrix configurations.
2Adaptability or versatility
If parallelism is mined only in the K dimension, then architecture universality is maintained, but computing performance deteriorates due to limited degree of parallelism
Solution Approach 1:
The patent merges the parallelism mining of K dimension and N dimension into a unified array processor architecture. Multiple processing units simultaneously exploit parallelism in both dimensions, combining the benefits of K-dimension parallelism (maintaining universality) with N-dimension parallelism (enhancing computing performance), thereby achieving both goals simultaneously.
Solution Approach 2:
The patent creates a dynamic parallelism exploitation mechanism where the array processor can flexibly allocate processing units to different dimensions based on the specific matrix dimensions and computational requirements. This dynamic adaptation allows the system to maintain universality for various matrix sizes while maximizing computing performance through optimized parallelism mining in both K and N dimensions.
3Productivity
If dedicated FPGA- or ASIC-based processor is used, then computing performance is improved, but device complexity and design cost increase
Solution Approach 1:
The patent designs a universal array processor architecture that can execute matrix multiplication operations with high computing performance while avoiding the complexity of dedicated FPGA- or ASIC-based designs. The array processor uses standard processing units that can be configured to handle different matrix dimensions and parallelism requirements, providing multi-functionality without the high design complexity and cost associated with dedicated hardware implementations.
Data Source
AI summary
A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an array processor having k processing units. The data bus is configured to sequentially read n columns of row vectors from an M×N multiplicand matrix and input same to each processing unit in the array processor, read an n×k submatrix from an N×K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation. Each processing unit in the array processor is configured to execute in parallel a vector multiplication operation on the input row and column vectors. Each processing unit includes a Wallace tree multiplier having n multipliers and n−1 adders. This implementation improves the processing efficiency of a matrix multiplication operation.