Fault-Tolerant Matrix Multiplication With Slice-Coded Recovery
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Solution Overview
Problem
Current fault-tolerant numerical linear algebra computations in parallel systems are inefficient due to high communication costs and require a significant increase in the number of processors, especially when handling soft and hard errors, and existing solutions do not adapt well to fast matrix multiplication algorithms.
Innovation Solution
A method and system that utilize a controller to split tasks among processors, assign additional processors for error correction, and employ slice-coded or posterior-recovery algorithms to minimize the number of additional processors and communication costs, while maintaining high performance and resource efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault-tolerant algorithms are implemented in parallel systems, then reliability is improved, but device complexity and communication costs increase significantly
Solution Approach 1:
The patent segments the fault tolerance mechanism into two distinct phases: (1) embedding error correction codes during the computation process using minimal additional processors, and (2) performing recovery operations only when faults are detected. This segmentation allows the system to maintain reliability while avoiding the continuous overhead of full fault-tolerant processor arrays, thus reducing device complexity.
Solution Approach 2:
The patent applies preliminary action by embedding error correction codes (such as parity bits or more sophisticated codes) into the data during the computation process. This preliminary encoding allows the system to detect and correct faults without requiring additional fault-tolerant processors, thereby reducing device complexity while maintaining reliability.
2Reliability
If fault-tolerant algorithms are implemented in parallel systems, then reliability is improved, but communication costs increase
Solution Approach 1:
The patent segments communication operations into regular computation-related communications and separate error correction code transmissions. By transmitting error correction codes sparsely and only when necessary (e.g., at checkpoint intervals or when faults are detected), the patent minimizes communication overhead while maintaining fault tolerance capability.
Solution Approach 2:
The patent uses lightweight, disposable error correction codes that can be quickly generated and transmitted without significant communication overhead. These codes act as temporary protective layers that are regenerated as needed, rather than requiring persistent, resource-intensive fault-tolerant communication protocols.
3Reliability
If error correction codes are generated and transmitted frequently, then reliability is improved, but productivity decreases due to overhead
Solution Approach 1:
The patent implements periodic action by generating and transmitting error correction codes at predetermined intervals (checkpoints) or triggered by specific events (detected anomalies), rather than continuously. This periodic approach ensures reliable fault detection while minimizing the overhead impact on computation efficiency, as the system can operate at full speed between checkpoint operations.
Solution Approach 2:
The patent enables self-service by incorporating error detection and correction capabilities directly into the computation flow, allowing the system to automatically identify and correct faults without external intervention. This self-service mechanism reduces the need for frequent external verification and recovery operations, thereby maintaining productivity while ensuring reliability.
Data Source
AI summary
A computer implemented method for performing fault tolerant numerical linear algebra computation task consisting of calculation steps that include at least classic or fast matrix multiplication, according to which, a controller splits the task among P processors, which operate in parallel. Additional processors are assigned according to execution and resources parameters, which are also used to select a slice-coded recovery algorithm or a posterior-recovery algorithm for executing the task. Pipelined-reduce operations are used to generate error correcting codes to protect the input blocks and outer products from faults. Upon detecting faults in one or more processors, if the slice-coded recovery algorithm has been selected, a slice-coded recovery algorithm is executed to recover lost input blocks and outer products that. If the posterior-recovery algorithm has been selected, error correcting codes are used for recovering lost input blocks and after the last step, recalculating outer products that correspond to faulty processors. In case when fast multiplication is needed, l DFS down-recursion steps are iteratively performed by the P processors and by the additional processors r times, for which the error correction codes will be valid, and after r times, recalculating the error correction codes for the next r times. Then by each processor of the P processors performs local block multiplication between a pair of blocks, while recalculating a new error correction code. Then the output matrix is created by iteratively performing d BFS up-recursion decoding steps on the multiplication product r times, the error correction codes will be valid only for the r times and after each group of r times, recalculating the error correction codes for the next r times, while at the end all iterations, blocks to be decoded obtaining and a code block that is held by the additional code processors, such that each processor holds a pair of blocks. Upon detecting faults in one or more processors, a recovery algorithm is executed, for recovering lost input blocks and multiplication results that correspond to faulty processors or correcting miscalculations of the processors by recalculation.