Matrix Multiplication Zero Skipping Logic

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Solution Overview

Problem

Existing matrix multiplication methods in graphics processing and artificial intelligence face inefficiencies due to large matrix sizes, particularly when dealing with zero-valued elements, which result in significant latency from unnecessary memory retrieval and processing.

Innovation Solution

Implementing a method that loads only non-zero elements of the vector into a cache for matrix multiplication, omitting the retrieval of rows corresponding to zero-valued elements, and using parallel processing to accelerate the multiplication of non-zero elements, thereby reducing latency and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If all elements of the vector are processed in matrix multiplication, then the computation is complete and accurate, but latency increases due to unnecessary memory retrieval of rows corresponding to zero-valued elements

Engineering Contradiction:
ImprovelatencyVSAvoidcomputation completeness
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent extracts and processes only the non-zero elements of the vector, omitting zero-valued elements entirely. This is achieved by identifying zero elements and skipping the retrieval and processing of corresponding rows from the matrix, thereby reducing memory access operations and latency while maintaining computation accuracy for the meaningful data.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a skipping mechanism that rapidly bypasses zero-valued elements in the vector during matrix multiplication. The system detects zero elements and skips the associated memory retrieval and processing steps, rushing through these unnecessary operations to reduce overall latency while preserving the integrity of computations involving non-zero elements.

Inventive Principle:
Principle #21Skipping (Rushing through)

2Productivity

If memory retrieval is performed for all vector elements, then data access is systematic and simple, but performance deteriorates due to unnecessary memory access for zero-valued elements

Engineering Contradiction:
ImproveperformanceVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the vector processing into distinct phases: identifying zero elements, skipping corresponding rows, and processing non-zero elements. This segmentation allows the system to selectively access only necessary memory locations, improving performance by eliminating redundant memory access while managing processing complexity through structured segmentation of the computation workflow.

Inventive Principle:
Principle #1Segmentation

3Productivity

If parallel processing is applied to all elements, then throughput is maximized, but resource utilization decreases due to parallel processing of zero-valued elements

Engineering Contradiction:
ImprovethroughputVSAvoidresource utilization
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by processing only the necessary non-zero elements in parallel, rather than all elements. This selective parallel processing maintains high throughput for meaningful computations while reducing resource utilization by excluding zero-valued elements from parallel processing operations, thereby optimizing the balance between throughput and energy consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12045306B2Multiplier with zero skipping
Publication Date: 2024.07.23 VERISILICON MICROELECTRONICS (SHANGHAI) CO LTD
  • US12045306B2 patent drawing
  • US12045306B2 patent drawing
  • US12045306B2 patent drawing

AI summary

A system performs matrix multiplication of a vector by a two-dimensional matrix by evaluating whether the vector includes zero values. Rows of the matrix are loaded into a first memory device from a second device. Rows corresponding to the indexes of the zero values are not loaded. A dot product of columns of the matrix and the input vector is performed and stored. The matrix may be stored in the second memory device such that only entries for non-zero entries are stored. The rows of the matrix may be reconstructed in the first memory device from these entries.