Matrix Multiplier Using Binary Quantization for Faster AI Computation
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Solution Overview
Problem
Existing matrix multiplication technologies are inefficient due to high computational requirements, which slows down artificial intelligence models and increases energy consumption.
Innovation Solution
A matrix multiplier and matrix multiplication device that employs binary coding quantization (BCQ) and quantization scale coefficients to reduce the computation amount and speed up matrix multiplication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional matrix multiplication is performed with high precision, then calculation accuracy is maintained, but computational load and operation time increase significantly
Solution Approach 1:
The patent applies binary coding quantization to transform weight parameters from continuous floating-point values to discrete binary values (-1 and +1). This parameter transformation reduces the computational complexity from O(N^3) floating-point operations to O(N^3) simplified operations that can be executed more efficiently, thereby improving operation speed while maintaining acceptable calculation accuracy through the use of quantization scale coefficients
Solution Approach 2:
The patent introduces quantization scale coefficients that are locally adapted to different regions or channels of the weight matrix. These scale coefficients preserve important local characteristics and variations in the data, allowing the system to maintain calculation accuracy in critical regions while benefiting from the speed improvements of binary quantization in other regions
2Productivity
If binary coding quantization is applied to reduce computation amount, then operation speed increases, but calculation precision may be reduced
Solution Approach 1:
The patent introduces quantization scale coefficients as intermediary parameters that bridge the gap between binary quantization and original precision requirements. These scale coefficients act as mediators that restore important magnitude information that is lost during binary quantization, thereby compensating for precision loss while maintaining the computational efficiency of binary operations
Solution Approach 2:
The patent creates a composite representation by combining binary quantized values with quantization scale coefficients. This composite approach leverages the speed advantages of binary arithmetic while incorporating the precision-preserving properties of scale coefficients, achieving a balanced solution that delivers both high operation speed and acceptable calculation accuracy
3Measurement precision
If standard floating-point multiplication is used, then calculation accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent transforms weight parameters from floating-point format to binary quantized format, which reduces the number of bits required for representation and processing. This parameter change enables the use of simpler, lower-power arithmetic operations that consume less energy while maintaining acceptable accuracy through the accompanying quantization scale coefficients
Data Source
AI summary
A matrix multiplier includes an input vector scaler configured to generate a first scaled input vector based on a first input vector and a plurality of quantization scale coefficients, a first data type converter configured to generate a first fixed-point scaled input vector based on the first scaled input vector, a processing element array including a first processing element configured to generate a first fixed-point output element based on the first fixed-point scaled input vector and first plurality of quantization sign values and a second processing element configured to generate a second fixed-point output element based on the first fixed-point scaled input vector and second plurality of quantization sign values, and a second data type converter configured to generate first and second output elements by converting data type of the first and second fixed-point output elements, and to output a first output vector including the first and second output elements.