Matrix Multiplier MAC Array With Float-Fixed Data Conversion

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Solution Overview

Problem

Deep learning operations, particularly matrix multiplication, consume significant computational resources and are challenging to implement efficiently in small semiconductor devices such as mobile or IoT devices due to the high computing power requirements.

Innovation Solution

A matrix multiplier and MAC operator are designed as a single piece of hardware that performs multiplication and accumulation operations using scaled input matrices and binary vectors, converting data types between floating-point and fixed-point formats to optimize performance in small semiconductors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If deep learning operations are implemented in small semiconductor devices, then computing power is reduced, but area occupied by matrix multiplier increases

Engineering Contradiction:
Improvecomputing powerVSAvoidarea occupied by matrix multiplier
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The matrix multiplier is divided into multiple MAC operators arranged in an array, where each MAC operator handles specific multiplication and accumulation operations. This segmentation allows the system to achieve high computing power through parallel processing while keeping each individual operator compact, thus reducing the overall area requirement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs data type conversion between floating-point and fixed-point formats to optimize the balance between precision and hardware resource usage. By dynamically changing data representation parameters, the system maintains adequate computational accuracy while reducing the area occupied by precision-related hardware components.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If data type conversion between floating-point and fixed-point is performed, then computational precision is improved, but device complexity increases

Engineering Contradiction:
Improvecomputational precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Data type converter units serve as intermediary components between floating-point input interfaces and the MAC operator array. These converters mediate the transformation between data formats, enabling precision optimization without requiring the entire device to handle complex floating-point operations, thus localizing complexity to specific conversion modules.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts data type conversion functionality into separate dedicated converter units, removing the complexity of floating-point handling from the core MAC operation logic. This extraction allows the main computation engine to operate with simpler fixed-point arithmetic while maintaining the ability to process floating-point data when needed.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If multiple MAC operators are integrated in a single piece of hardware, then integration density is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The matrix multiplier is segmented into multiple identical or modular MAC operators that can be systematically arranged in an array. This modular segmentation allows for standardized manufacturing processes where each unit follows the same design template, reducing the cumulative effect of manufacturing variations and making high integration density more achievable with standard precision requirements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4592823A1Multiplication and accumulation operator and matrix multiplier including the same
Publication Date: 2025.07.30 SAMSUNG ELECTRONICS CO LTD
  • EP4592823A1 patent drawingFigure 1
  • EP4592823A1 patent drawingFigure 2
  • EP4592823A1 patent drawingFigure 3

AI summary

A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scale factors, a first data type converter configured to convert the data type of the scaled input matrix to fixed-point and generate a fixed-point input matrix, a multiplication and accumulation operator array configured to receive the fixed-point input matrix and a plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate the first input matrix and the second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix, and a second data type converter configured to convert the data type of the fixed-point output matrix to a floating point and generate a second output matrix.