Matrix Multiply Outer Product Sum Hierarchical Network
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Solution Overview
Problem
Conventional matrix multiplication techniques are ill-suited for hierarchical networks, leading to load imbalance and inefficient use of underlying CU networks, causing some processor cores to stall and inefficient data communication.
Innovation Solution
The method maps matrix multiplication computations as a sum of partial outer products to a hierarchical CU network, exploiting physical proximity and asymmetric communication links to localize communication and reduce data transfer between closely located processor cores, thereby decreasing load imbalance and data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional matrix multiplication techniques are used in hierarchical networks, then the computation can be performed in parallel across multiple processor cores, but load imbalance occurs causing some processor cores to stall and efficiency decreases
Solution Approach 1:
The patent segments the matrix multiplication computation into distinct outer product operations that can be independently assigned to processor cores. By dividing the computation into smaller, independent tasks (outer products of matrix columns and rows), the system achieves better load distribution across the hierarchical network, preventing processor stalling while maintaining parallel execution efficiency.
2Productivity
If data is communicated between distant processor cores in hierarchical networks, then computation can proceed, but communication time increases and efficiency decreases
Solution Approach 1:
The patent optimizes data communication by localizing it to physically closer processor cores within the hierarchical network. By restructuring the computation as outer products, data can be exchanged between nearby cores rather than distant ones, reducing communication time and improving overall computation speed while maintaining correctness.
3Adaptability or versatility
If conventional matrix multiplication is mapped to hierarchical CU networks, then the operation can be executed, but data communication between processor cores is inefficient and load imbalance occurs
Solution Approach 1:
The patent inverts the conventional approach by expressing matrix multiplication as a sum of outer products rather than using traditional dot-product methods. This inversion allows for more efficient data communication patterns in hierarchical networks, where columns of one matrix and rows of another can be distributed and processed in a manner that better utilizes the network structure, improving communication efficiency and adapting to hierarchical architectures.
Data Source
AI summary
A processing device is provided which includes memory and a processor comprising a plurality of processor cores in communication with each other via first and second hierarchical communication links. Each processor core in a group of the processor cores is in communication with each other via the first hierarchical communication links. Each processor core is configured to store, in the memory, one of a plurality of sub-portions of data of a first matrix, store, in the memory, one of a plurality of sub-portions of data of a second matrix, determine an outer product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core of the group of processor cores, another sub-portion of data of the second matrix and determine another outer product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.