Matrix Phase Comparator for Low-Jitter PLL Clock Recovery
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Solution Overview
Problem
High-speed chip-to-chip communication systems face challenges in maintaining accurate phase locked loops due to increased circuit node capacitance and parasitic delays, which constrain loop response bandwidth and introduce jitter and noise, limiting the stability and accuracy of clock recovery in Phase-Locked Loops (PLLs).
Innovation Solution
The integration of a matrix phase comparator and phase interpolator within the PLL, utilizing multiple phase comparisons and weighted summations to enhance loop stability and bandwidth, reduces node capacitance and enables improved power supply noise rejection, leading to lower clock jitter and increased lock bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed multi-wire interface is used for chip-to-chip communication, then communication speed and bandwidth are improved, but circuit node capacitance and parasitic delays increase, constraining loop response bandwidth and introducing jitter and noise
Solution Approach 1:
The phase detector is divided into multiple parallel phase detection paths, each handling a subset of the multi-wire interface signals. This segmentation allows the system to process high-speed signals in parallel while reducing the capacitive load on any single node, thereby maintaining PLL stability at high communication speeds.
Solution Approach 2:
The patent transitions from single-ended phase detection to a multi-dimensional approach by utilizing multiple differential pairs and creating a matrix of phase detection elements. This dimensional expansion allows simultaneous processing of multiple wires, improving communication bandwidth while distributing parasitic effects across multiple nodes to maintain loop stability.
2Device complexity
If conventional phase detector is used, then circuit simplicity is maintained, but loop response bandwidth is constrained and jitter and noise are introduced
Solution Approach 1:
Multiple phase detection paths are merged into a unified phase error signal through weighted summation. This combining approach maintains relative circuit simplicity while achieving improved phase detection accuracy and expanded loop bandwidth by leveraging signals from multiple wires simultaneously.
Solution Approach 2:
The phase detector circuit is designed to handle multiple functions: it processes multiple differential pairs, performs phase comparison across different wires, and generates a composite phase error signal. This multi-functionality allows the same circuit structure to improve both measurement precision and loop response bandwidth without proportionally increasing complexity.
3Reliability
If multiple phase comparisons with weighted summation are implemented, then loop stability and bandwidth are improved, but node capacitance increases
Solution Approach 1:
Different regions of the phase detector circuit are optimized with different properties: early stage comparison elements use minimal capacitance designs, while later summation stages use higher impedance nodes. This local quality optimization allows multiple phase comparisons to be performed while controlling overall node capacitance to maintain loop stability.
Data Source
AI summary
Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.