Matrix Processor Unit Convolution Mapping
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Solution Overview
Problem
Current hardware solutions for neural networks face challenges in efficiently computing convolution operations, particularly depthwise convolutions, due to complexity and limitations in optimizing matrix operations, leading to suboptimal performance and efficiency.
Innovation Solution
A processor system with a matrix processor unit capable of performing matrix operations using vector units, which unrolls input matrices into vectors, allowing for parallel processing and efficient computation of convolution operations through vector multiplication and addition, reducing the need for complex memory organization schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional optimization approaches for depthwise convolution are used, then convolution performance is improved, but device complexity and memory organization complexity increase
Solution Approach 1:
The matrix processor unit is designed to perform multiple matrix operations (matrix-matrix multiplication, matrix-vector multiplication, vector-dot product) using the same hardware architecture, eliminating the need for specialized depthwise convolution hardware while maintaining high performance through unified parallel processing capabilities
Solution Approach 2:
The invention changes the operational parameters of the matrix processor unit by configuring it to handle convolution operations through standard matrix multiplication routines, adjusting data flow patterns and memory access schemes to optimize for convolution workloads without requiring specialized hardware structures
2Speed
If specialized hardware is used for depthwise convolution, then computation speed is improved, but adaptability to different matrix operations decreases
Solution Approach 1:
The matrix processor unit provides a universal platform that can execute various matrix operations including convolution, matrix multiplication, and vector operations through the same hardware, achieving both high speed for convolution and broad adaptability to different computational tasks
3Productivity
If complex memory organization schemes are implemented, then convolution efficiency is improved, but ease of manufacture and system simplicity deteriorate
Solution Approach 1:
The invention uses standard memory organization schemes that can be implemented with conventional memory structures, achieving high convolution efficiency through optimized access patterns rather than through complex specialized memory architectures, thereby simplifying manufacturing and system implementation
Data Source
AI summary
A system comprises a matrix processor unit that includes a first type of register, a group of a second type of registers, and a plurality of calculation units. The first type of register is configured to concurrently store values from different rows of a first matrix. At least a portion of the first type of register is logically divided into groups of elements, and each of the groups corresponds to a different row of the first matrix. Each of the second type of registers is configured to concurrently store values from a plurality of different rows of a second matrix. Each of the calculation units corresponds to one of the second type of registers and is configured to at least in part determine a corresponding element in a result matrix of convoluting the second matrix with the first matrix.