Programmable Logic Cell Matrix with Distance-Range Routing Multiplexers

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Solution Overview

Problem

Conventional field programmable gate arrays (FPGAs) experience inefficient use of cells due to the Manhattan routing pattern, leading to suboptimal signal routing and resource utilization.

Innovation Solution

A matrix of programmable cells with dedicated routing multiplexers for different non-overlapping ranges of distances, allowing flexible connections and efficient logic function implementation with a reduced number of routing multiplexers, where each multiplexer's inputs are coupled to outputs within specific distance ranges, and additional multiplexers are used for overlapping ranges, primarily connecting cells within the same row or column.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If Manhattan routing pattern is used for signal routing in conventional FPGAs, then routing simplicity is maintained, but cell utilization efficiency deteriorates

Engineering Contradiction:
Improverouting simplicityVSAvoidcell utilization efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The routing system is segmented into multiple banks of routing multiplexers, where each bank handles routing to cells at specific distance ranges. This segmentation allows different routing paths to be optimized independently, improving cell utilization while maintaining routing simplicity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different routing multiplexers are configured with different connection ranges tailored to local routing needs. Cells at different distances from a source cell can access appropriate routing multiplexers optimized for their specific distance requirements, improving overall routing efficiency without compromising simplicity.

Inventive Principle:
Principle #3Local quality

2Device complexity

If routing multiplexers are connected to neighboring cells only, then routing complexity is reduced, but connection flexibility deteriorates

Engineering Contradiction:
Improverouting complexityVSAvoidconnection flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

Each routing multiplexer is designed with universal input connections that can receive signals from multiple distance ranges. This multi-functionality allows a single routing multiplexer to serve both nearby and distant cells, providing connection flexibility while keeping the overall routing structure manageable and not excessively complex.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The routing architecture adds a distance-range dimension to the traditional grid structure. By organizing routing multiplexers into banks that handle different distance ranges, the system achieves flexible long-distance connections without proportionally increasing routing complexity, as the distance dimension is managed through hierarchical banking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If more routing multiplexers are provided for long-distance connections, then connection range is extended, but number of routing multiplexers increases

Engineering Contradiction:
Improveconnection rangeVSAvoidnumber of routing multiplexers
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Instead of providing dedicated routing multiplexers for every possible long-distance connection, the system uses copies of routing multiplexer units organized in banks. Each bank contains multiple instances of similar routing multiplexer circuits that handle different distance ranges, reducing the total number of unique routing multiplexer designs while extending connection range through systematic replication.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS7795912B2Circuit comprising a matrix of programmable logic cells
Publication Date: 2010.09.14 NXP BV
  • US7795912B2 patent drawing
  • US7795912B2 patent drawing
  • US7795912B2 patent drawing

AI summary

An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).