Matrix Scan Clock Sequencing to Limit Scan Test Power Surges

The patent applies periodic action by implementing a matrix scan architecture that sequentially activates different groups of scan chains in alternating phases. Instead of applying all scan shift clocks simultaneously, the system divides scan chains into multiple groups and activates them in alternating time intervals, creating a periodic pattern of clock activation that spreads power consumption over time while maintaining high test throughput.

The patent segments the scan chain system into multiple independent groups, each controlled by its own scan shift clock. This segmentation allows different groups to be activated at different times, preventing simultaneous power consumption surges. The matrix architecture organizes scan chains in a structured segmented manner that enables controlled activation patterns.

The matrix scan architecture implements periodic action by alternating activation between multiple groups of scan chains. This periodic pattern allows the system to maintain high overall throughput by keeping multiple groups ready and alternating their activation, rather than extending the duration of individual scan tests. The periodic switching between groups distributes power consumption while maintaining productivity.

The patent ensures continuity of useful action by having multiple groups of scan chains prepared and ready, with alternating activation patterns. While one group is being tested, another group can be prepared or is being tested in parallel phases. This continuous alternating action maintains high throughput without requiring extended individual test durations.

The patent applies merging by combining multiple scan shift clock signals into a smaller number of physical pins using multiplexing techniques. The matrix architecture allows multiple clock groups to share common pin structures, and clock signals are time-multiplexed through shared pins. This merging approach enables multiple scan chains to be controlled with fewer physical pins than would be required if each clock had its own dedicated pin.

The patent implements universality by designing pin structures that serve multiple functions. Pins are configured to handle multiple scan shift clock signals at different time intervals, and the matrix architecture allows the same pin infrastructure to support multiple scan chain groups. This multi-functional pin design eliminates the need for dedicated pins for each clock signal, staying within pin count limitations.