Matrix Sensor Time Coding Bus Access Priority Logic
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Solution Overview
Problem
Time-coded image sensors face challenges with high energy consumption and hardware complexity due to arbitration mechanisms needed to manage pixel collisions during asynchronous reading, which can degrade image quality.
Innovation Solution
Implementing a system with fixed priorities and a mechanism for counting reinitializations to avoid information loss during conflicts, where detection elements have different bus access priority levels and logic circuits manage bus access attempts and reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an arbitration mechanism (such as AER protocol) is used to manage pixel collisions during asynchronous reading, then collision resolution is improved, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent extracts the arbitration function from a complex centralized controller and distributes it to individual pixel circuits through simple priority logic and request/acknowledge signals. Each pixel circuit independently manages bus access based on its priority level, eliminating the need for a complex global arbiter while maintaining collision resolution.
Solution Approach 2:
The arbitration mechanism is segmented into multiple independent pixel circuits, each with its own priority logic and bus access control. Instead of a single centralized arbiter, multiple simple segments work in parallel, reducing overall system complexity while maintaining reliable collision resolution through distributed decision-making.
2Reliability
If an arbitration mechanism is used to manage pixel collisions, then collision resolution is improved, but power consumption increases significantly
Solution Approach 1:
The patent removes the power-intensive centralized arbiter and replaces it with low-power distributed priority logic in each pixel circuit. The simplified request/acknowledge mechanism consumes minimal energy compared to full arbitration protocols, directly reducing overall system power consumption while maintaining collision resolution capability.
Solution Approach 2:
The system dynamically adjusts bus access based on real-time priority levels and collision detection, allowing only necessary arbitration actions to occur. This dynamic approach prevents continuous high-power arbitration operations, reducing average power consumption while maintaining reliable collision resolution when needed.
3Device complexity
If fixed priorities with reset counting mechanism are used instead of arbitration, then energy consumption and hardware complexity are reduced, but information loss may occur during conflicts
Solution Approach 1:
The patent implements a feedback mechanism where pixels receive acknowledgment signals from the bus controller, allowing them to detect when their address transmission was successful or blocked. This feedback enables the reset counting mechanism to accurately track conflicts and determine when information loss occurred, allowing for proper error handling without complex arbitration logic.
Solution Approach 2:
The system performs preliminary actions by pre-establishing fixed priority levels for all pixels before operation begins. This preliminary ordering eliminates the need for real-time arbitration decisions, reducing complexity while the reset counting mechanism provides a pre-planned method for handling conflicts that prevents information loss through systematic retry protocols.
Data Source
Figure 1~2a
Figure 2b~2d
Figure 3~5e
AI summary
Matrix sensor comprising a matrix of sensing elements (PX) arranged by rows and columns and a readout circuit for each column, the elements of the same column being connected to the corresponding readout circuit via a bus (B), each element comprising a sensor (PHD), a charge integrator (INT) configured to accumulate charges generated by the sensor, a comparator (CMP) configured to generate a trigger signal (FL) when a voltage level (V) across the latter reaches a threshold level, and a bus access logic circuit (CLA) configured to receive said trigger signal as input and attempt to transmit on said bus an address (APX) of said element in the column, characterized in that the elements of the same column have predetermined bus access priority levels,and in that said bus access logic circuit of each element is configured to: refrain from transmitting said address and cause a reset of the load integrator of the sensing element if the bus is preempted by a higher priority level element; count the number of attempts made before it can transmit said address; and communicate said number to said read circuit along with said element address.