Matrix Splitting Circuit for Analog Neural Network Computation
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Solution Overview
Problem
Current computing systems face challenges in efficiently processing big data, particularly with artificial neural networks, due to the difficulty in performing vector-matrix multiplications involving negative elements, which are typically not supported by analog computation methods using memristor memory cells.
Innovation Solution
The system splits matrices and vectors into positive and negative components, applies an offset to convert negative elements into non-negative values, and uses these components to perform vector-matrix multiplications in separate sub-arrays within the computation memory, allowing for analog computation and correction of results to handle negative elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog computation methods using memristor memory cells are used for vector-matrix multiplications, then computation speed is improved, but the ability to process negative elements is lost
Solution Approach 1:
The patent divides the computation process into separate segments: one for handling positive elements and another for handling negative elements. By splitting the vector-matrix multiplication into distinct processing paths for positive and negative values, the system maintains analog computation speed while recovering the ability to process negative elements through structured segmentation of the computational workflow.
Solution Approach 2:
The patent introduces intermediary components including a negative number computation control circuit that acts as a mediator between the analog computation memory and the digital processing units. This intermediary circuit receives negative elements, converts them to a format suitable for analog computation, and manages the coordination between digital control and analog execution, thereby enabling negative element processing without sacrificing computation speed.
2Adaptability or versatility
If matrices are split into positive and negative components and processed separately, then the ability to handle negative elements is improved, but device complexity increases
Solution Approach 1:
The patent designs the negative number computation control circuit to perform multiple functions: it identifies negative elements, generates offset vectors, controls the splitting of matrices into positive and negative components, and manages the recombination of results. By making this control circuit multi-functional, the patent handles negative elements effectively while minimizing the need for additional separate components, thus controlling device complexity.
Solution Approach 2:
The patent merges the control functions for positive and negative element processing into a unified control architecture. The negative number computation control circuit integrates the logic for offset vector generation, matrix splitting control, and result recombination into a single coordinated system, reducing overall device complexity compared to having completely separate processing paths for positive and negative elements.
3Adaptability or versatility
If offset vectors are generated and applied to convert negative elements into non-negative values, then processing capability for negative elements is improved, but computation time increases
Solution Approach 1:
The patent performs preliminary actions by pre-calculating offset vectors and preparing the splitting of matrices into positive and negative components before the main analog computation begins. The negative number computation control circuit generates offset vectors in advance and configures the memory structure to accommodate separated positive and negative elements, so that during the actual analog multiplication, no additional time-consuming conversions are needed, thus minimizing computation time overhead.
Data Source
AI summary
A data processing system may include: a matrix splitting circuit configured to: split the matrix into a positive matrix and a negative matrix, and store the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively; a vector conversion circuit configured to generate an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element, and apply the offset vector to the row lines of the first sub array and the second sub array; and an offset correction circuit configured to generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix, and subtract the offset correction value from a computation value outputted from the first sub array and the second sub array,