Matrix Stripe Cache for RAID I/O Performance

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Solution Overview

Problem

RAID systems exhibit poor performance for small write operations and fragmented sequential writes due to complex implementation and overhead in both normal and degraded modes, failing to maximize disk performance and efficiently handle discontiguous data storage.

Innovation Solution

The implementation of a Matrix Stripe Cache (MSC) using a rxw-matrix for contiguity transform, which generates transformed read and write operations to destage data more efficiently, optimizing I/O performance by inserting additional operations between discontiguous reads and writes within predetermined distances, and managing cache operations to improve sequential and bulky I/Os.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional RAID destage algorithms are used, then data can be stored with redundancy and basic I/O operations can be performed, but I/O performance for small writes and fragmented sequential writes is poor due to complex implementation and overhead

Engineering Contradiction:
ImproveI/O performanceVSAvoidimplementation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the RAID destage operation into two independent phases: read phase and write phase. The read phase reads data and parity from disks into cache, and the write phase writes updated data and recalculated parity back to disks. This segmentation eliminates the complex coordination required in traditional algorithms, reducing implementation complexity while improving I/O performance through better utilization of disk bandwidth and cache resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-reading all required data and parity blocks into cache before any write operations begin. This preliminary action allows the system to prepare all necessary data in memory, reducing the number of disk I/O operations needed during the actual write phase and thereby improving overall I/O performance without adding significant implementation complexity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If traditional RAID destage algorithms are used, then data redundancy is maintained, but the number of I/O operations is high leading to poor performance for fragmented writes

Engineering Contradiction:
Improvewrite performanceVSAvoidI/O operation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple scattered write operations into a single consolidated destage operation. When multiple fragmented writes occur, the system waits until a threshold is reached or a timeout occurs, then performs a single batched destage operation that handles all pending writes together. This merging reduces the total number of I/O operations and their associated timing overhead, significantly improving write performance for fragmented sequential writes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent maintains continuity of useful action by keeping data in cache between write operations rather than immediately writing to disk. The destage operation continues to accumulate and process writes without interruption, utilizing disk bandwidth more efficiently by performing sustained sequential I/O operations rather than frequent small random I/O operations, thereby reducing total I/O time.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If conventional RAID read operations are performed, then data can be read from disks, but read performance in degraded mode suffers due to complex parity reconstruction operations

Engineering Contradiction:
Improveread performanceVSAvoiddegraded mode operation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary action by pre-calculating and storing parity information in cache during normal operation. When a disk failure occurs and read operations must be performed in degraded mode, the required parity data is already available in cache, eliminating the need for complex real-time parity reconstruction operations across remaining disks. This preliminary preparation maintains high read performance even in degraded mode while preserving data reliability through the pre-computed parity information.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7861035B2Method of improving input and output performance of raid system using matrix stripe cache
Publication Date: 2010.12.28 KOREA ADVANCED INST OF SCI & TECH
  • US7861035B2 patent drawing
  • US7861035B2 patent drawing
  • US7861035B2 patent drawing

AI summary

A method of improving the Input/Output (I/O) performance of a Redundant Array of Independent Disks (RAID) system using a Matrix Stripe Cache (MSC). The method includes a first step of generating a rxw matrix, that is, a read and write matrix, present before row combination, through a unit MSC that will perform writing on a disk, a second step of generating a rxw matrix, that is, a final read and write matrix, from the rxw matrix present before row combination, which is generated at the first step, through row combination, and a third step of performing reading based on the row-combined rxw matrix generated at the second step, performing an XOR operation on the row-combined rxw matrix on a row basis, and performing writing on the row-combined rxw matrix on a column basis.