Matrix Time-to-Digital Conversion for High-Resolution Delay Measurement
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Solution Overview
Problem
Existing time difference measurement techniques using Vernier scales face limitations due to the minimum manufacturable delay value, leading to increased uncertainty and the need for a large number of delay elements, which can result in significant errors in high-resolution time difference measurements.
Innovation Solution
A time-to-digital converter (TDC) system that includes multiple delay elements for both reference and clock signals, with a matrix memory to encode time delay differences, and a frequency synthesizer that uses a digitally controlled oscillator and digital filter to generate a digital control word, enabling high-resolution time difference measurement with reduced uncertainty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Vernier techniques are used to achieve high-resolution time difference measurements, then measurement precision is improved, but the number of delay elements required increases significantly
Solution Approach 1:
The patent transitions from a single-scale Vernier measurement approach to a two-dimensional matrix structure where multiple delay lines (different dimensions) are combined. This matrix architecture allows high-resolution time difference measurement with fewer elements by exploiting the dimensional relationship between reference and measurement delay lines, effectively converting a one-dimensional problem into a two-dimensional solution space.
2Measurement precision
If the number of delay elements is increased to achieve high-resolution measurements, then measurement precision is improved, but uncertainty in time difference measurement increases
Solution Approach 1:
The patent creates multiple copies of delay elements arranged in a matrix structure where reference delay lines and measurement delay lines are replicated. This copying approach allows redundant measurements and comparisons across multiple paths, reducing uncertainty through statistical averaging while maintaining high resolution. The matrix structure provides multiple identical measurement channels that can be combined to reduce random errors.
3Device complexity
If minimum manufacturable delay value is used in Vernier techniques, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent segments the time difference measurement function across multiple delay elements arranged in a matrix, where each element contributes a portion of the total measurement capability. Instead of relying on a single large delay element or few elements with large individual delays, the measurement function is divided and distributed across many smaller delay elements, each with minimum manufacturable delay values. This segmentation allows high overall resolution while using only minimal individual delay elements.
Data Source
AI summary
The present disclosure provides for a time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparators 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.