Matrix Tiling for Sparse Matrix Computation
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Solution Overview
Problem
Conventional approaches, including CPUs, GPUs, and CMOS logic circuits, are inefficient in solving computationally difficult problems like NP-hard problems due to the high hardware, power, and time requirements for processing sparse matrices, which contain many redundancies.
Innovation Solution
The technology identifies unique submatrices within redundant matrices and processes only one copy of each, using a hardware accelerator with a recursive neural network to generate outputs based on submatrix locations, reducing hardware, power, and time consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional approaches (CPU, GPU, CMOS logic circuits) are used to process sparse matrices, then the problems can be solved, but the hardware requirements, power consumption, and time requirements are excessively high
Solution Approach 1:
The patent extracts and processes only the unique submatrices from the redundant sparse matrix, separating the essential computational content from the redundant data. This extraction principle reduces the volume of data that needs to be processed, thereby decreasing power consumption and computation time while maintaining solution accuracy.
Solution Approach 2:
The patent segments the large sparse matrix into multiple submatrices, identifies unique ones, and processes them separately. This segmentation allows the system to handle only the necessary computational units, reducing overall hardware requirements and power consumption while improving computational efficiency.
2Reliability
If conventional approaches process sparse matrices, then complete computation is achieved, but the hardware complexity and resource requirements increase significantly
Solution Approach 1:
By extracting only the unique submatrices from the sparse matrix, the patent reduces hardware complexity while maintaining computational accuracy. The extraction eliminates redundant processing units that would otherwise be required, simplifying the hardware architecture without compromising the ability to solve the computational problem correctly.
3Productivity
If all submatrices in a redundant matrix are processed, then complete solution is obtained, but the processing time and computational resources are wasted on redundant copies
Solution Approach 1:
The patent extracts the unique submatrices from the redundant set and processes only those, eliminating wasted processing time on duplicate copies. This extraction approach maintains computational efficiency and solution completeness while significantly reducing the time lost to redundant operations.
Solution Approach 2:
The patent performs preliminary identification and extraction of unique submatrices before the main processing stage. This preliminary action prevents the system from wasting time processing redundant copies during the main computation, thereby improving overall processing efficiency and reducing total computation time.
Data Source
AI summary
a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.