Matrix Timing Detection Circuit Segmentation for Speed and Resolution
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Solution Overview
Problem
Existing timing detection circuits face challenges in improving resolution and detection speed, particularly in converting clock cycles into digital codes, due to limitations in delay element delay time and recovery periods.
Innovation Solution
The proposed timing detection circuit divides column lines into multiple sets, using NAND circuits for logical operations and reducing parasitic capacitance, allowing for improved resolution and high-speed detection without increasing the number of column latches or shortening the detection period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If delay element delay time is shortened to improve detection speed, then detection speed increases, but resolution of timing detection deteriorates
Solution Approach 1:
The column lines are divided into multiple sets (first set and second set), allowing the timing detection circuit to process different groups of delay elements separately. This segmentation enables the circuit to maintain high detection speed while preserving resolution by systematically managing the discharge and recovery processes across multiple column line sets.
Solution Approach 2:
The circuit performs preliminary charging of column lines before detection operations. By ensuring column lines are fully charged before each detection cycle and managing their discharge timing, the circuit maintains signal integrity and resolution even when delay element times are shortened for faster detection.
2Measurement precision
If recovery period is extended to improve resolution, then resolution improves, but detection speed decreases
Solution Approach 1:
By dividing column lines into multiple sets that can operate in different phases, the circuit achieves overlapping operation cycles. While one set of column lines is being charged for the next detection cycle, another set is being discharged or is in recovery, thereby extending the effective recovery period without increasing the overall detection cycle time.
Solution Approach 2:
The circuit maintains continuous detection operations by managing multiple column line sets in different operational states simultaneously. This continuity allows the system to achieve high detection speed while ensuring each column line set has adequate recovery time, as the discharge and recovery processes are distributed across multiple sets rather than sequential.
3Speed
If parasitic capacitance is reduced to improve detection speed, then detection speed increases, but manufacturing complexity increases
Solution Approach 1:
The division of column lines into multiple sets with dedicated NAND circuits for each set allows for modular design and systematic reduction of parasitic capacitance. Each set can be optimized independently, making the manufacturing process more manageable despite the increased number of components.
Solution Approach 2:
The circuit design changes the electrical parameters by introducing multiple column line sets with controlled capacitance values. This parameter change approach allows optimization of detection speed through reduced parasitic capacitance while maintaining manufacturability through systematic design rules and standardized circuit blocks.
Data Source
AI summary
A timing detection circuit includes: a delay circuit in which a plurality of cascade connected delay elements are arranged in a matrix; a plurality of odd-numbered row column lines provided in each column for each set by dividing odd-numbered rows into a plurality of sets; a plurality of even-numbered row column lines provided in each column for each set by dividing even-numbered rows into a plurality of sets; a first logical operation circuit performs a logical operation on levels of the odd-numbered row column lines and outputs a first operation result to a second latch; a second logical operation circuit performs a logical operation on levels of the plurality of even-numbered row column lines and outputs a second operation result to a third latch; and a control circuit given the first operation result and controls charging of the odd-numbered and even-numbered row column lines based on the second clock.