Streaming Matrix Transformation Circuit for Multi-Dimensional Transposition
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Solution Overview
Problem
Conventional deep learning accelerators face challenges in achieving high-performance and low-cost matrix transformation, particularly in supporting multiple matrix transformations like transposition of two-dimensional and three-dimensional matrices, and dimension expansion, due to inefficient hardware design and high register consumption.
Innovation Solution
The proposed solution involves an apparatus with a first shift unit for cyclically shifting matrix data, a cache unit for rearranging data storage, and a second shift unit for further cyclic shifting, enabling efficient transformation of multi-dimensional matrices with characteristics of streaming, simple circuit, and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hardware design is used for matrix transformation, then basic transformation functions can be achieved, but the circuit complexity and power consumption increase significantly
Solution Approach 1:
The matrix transformation apparatus is divided into three functional segments: a first shift unit for row-wise cyclic shifting, a cache unit for column-wise storage, and a second shift unit for column-wise cyclic shifting. This segmentation allows each unit to perform a specific transformation operation independently, reducing overall circuit complexity while maintaining versatility for multiple transformation types.
Solution Approach 2:
The apparatus uses universal shift units that can perform different cyclic shifting operations depending on control signals. The same shift unit structure handles both row-wise and column-wise transformations by changing the shift direction and amount, eliminating the need for separate dedicated circuits for each transformation type.
2Productivity
If conventional hardware design is used for matrix transformation, then transformation operations can be performed, but power consumption becomes high
Solution Approach 1:
The design replaces complex combinatorial logic circuits with sequential shift operations controlled by simple control signals. Instead of using complex routing switches and multiplexers, the patent uses register shift operations that are inherently more energy-efficient, achieving high-speed transformation with reduced power consumption.
Solution Approach 2:
The apparatus performs matrix transformation in a continuous streaming manner where data flows through the shift units and cache in a pipeline. This continuous operation avoids repeated setup and teardown of transformation paths, maintaining high productivity while reducing the energy required for each transformation operation.
3Adaptability or versatility
If conventional hardware design is used for matrix transformation, then transformation can be achieved, but register consumption increases
Solution Approach 1:
The patent handles multi-dimensional matrix transformations by treating different dimensions sequentially. The cache unit stores intermediate results in a structured format that allows the same shift units to operate on different dimensions by changing the shift parameters, supporting 2D, 3D, and higher-dimensional transformations without proportionally increasing register usage.
4Use of energy by stationary object
If simple circuit design is used, then power consumption is low, but the ability to support multiple matrix transformations is limited
Solution Approach 1:
The shift units are designed to be dynamically controllable, where the shift amount and direction are determined by control signals rather than fixed hardware configuration. This dynamic control allows the same simple circuit structure to adapt to different transformation requirements (transposition, dimension expansion, rotation) without increasing circuit complexity or power consumption.
Data Source
AI summary
Disclosed are an apparatus and method for transforming a matrix, and a data processing system. The apparatus may include: a first shift unit, configured to receive matrix data and perform first cyclic shift on the matrix data to generate first data; a cache unit, configured to write each row of data into the cache unit in the first data thereto in an order different from the order of respective data in the row of data to store the first data as second data; and a second shift unit, configured to read the second data from the cache unit and perform second cyclic shift on the second data to generate transformed matrix data.