Matrix Transposing Circuit Sub-Matrix Segmentation
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Solution Overview
Problem
Existing matrix transposing circuits in video image processing, such as those used in AVC and HEVC, face inefficiencies in performing multiple matrix transform operations due to the need for extensive memory banks and complex shifting operations, particularly when handling large matrices like 16×16 or 32×32 2D DCT/IDCT operations.
Innovation Solution
A matrix transposing circuit that divides a N×N matrix into sub-matrices, utilizing an m×N input register array and an N×m output register array, where N, m, and n are powers of 2, allowing for efficient storage and retrieval of data across multiple RAM blocks, enabling the transposition of matrices by shifting data in specific directions to achieve the transpose operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If extensive memory banks are used for matrix transposing operations, then the capacity to handle large matrices is improved, but the device complexity increases
Solution Approach 1:
The patent divides the N×N matrix into multiple sub-matrices of size m×n, where N=n×m×b. Each sub-matrix is processed independently through the register arrays and storage blocks, breaking down the complex operation of handling large matrices into manageable segments. This segmentation reduces the complexity of memory bank configuration while maintaining the capacity to handle large matrices.
2Manufacturing precision
If complex shifting operations are implemented for matrix transposition, then the transposition accuracy is improved, but the operation time increases
Solution Approach 1:
The patent performs preliminary organization of matrix elements into structured formats within the register arrays before the actual transposition operation. The input register array organizes elements in a specific pattern that facilitates efficient shifting, and the output register array is pre-configured to receive and arrange transposed elements. This preliminary action reduces the complexity and time of the shifting operations while maintaining transposition accuracy.
3Productivity
If multiple storage blocks are used for data retrieval, then the data access efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple storage blocks (b storage blocks) into a unified memory structure that works协同 with the register arrays. The storage blocks are merged in such a way that they collectively provide efficient data access for matrix transposition operations, with each block handling specific portions of the matrix data. This merging approach improves data access efficiency while managing the complexity through a systematic organization scheme.
Data Source
AI summary
The disclosure provides a matrix transposing circuit for outputting a transposed N×N matrix. The matrix transposing circuit includes: an input resister array with m×N array; a memory having b storage blocks; an output register array with N×m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n×m×b. The matrix is divided into multiple sub-matrixes with m×n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.