Matrix Transposition in Multiplication Array Circuitry
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Solution Overview
Problem
Current graphics processing units (GPUs) face limitations in efficiently processing general-purpose computations and machine-learning operations due to their fixed function units and lack of parallel processing capabilities for diverse operations beyond graphics rendering.
Innovation Solution
A general-purpose GPU architecture is developed, incorporating a parallel processing unit with a scheduler and multiple processing clusters that can execute parallel threads, enabling efficient processing of general-purpose computations and machine-learning operations through SIMT architecture and dedicated circuitry for matrix operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed function computational units are used in GPUs, then graphics rendering operations can be performed, but the processor cannot efficiently handle general-purpose computations and machine-learning operations
Solution Approach 1:
The patent implements a universal matrix multiplication engine that can perform both traditional graphics rendering operations and general-purpose computations including machine-learning operations. The engine uses a unified architecture with configurable parameters to handle diverse operation types without requiring separate specialized hardware units, thereby achieving multi-functionality while maintaining high processing efficiency
2Productivity
If parallel processing capabilities are added for diverse operations, then general-purpose computations and machine-learning operations can be processed efficiently, but the device complexity increases
Solution Approach 1:
The patent segments the matrix multiplication engine into distinct functional components including an input interface unit, a matrix multiplication unit, and an output interface unit. Each component has a specific function, allowing the complex parallel processing capability to be built from simpler modular units, thereby managing device complexity while achieving high processing efficiency for diverse operations
3Adaptability or versatility
If matrix multiplication engine is implemented without transposition buffer, then the engine can perform basic matrix operations, but it cannot efficiently support diverse matrix operations requiring transposition
Solution Approach 1:
The patent introduces a transposition buffer as an intermediary component between the matrix multiplication unit and the output interface. This buffer enables the engine to efficiently perform diverse matrix operations including transposition and accumulation by temporarily storing intermediate results, thereby enhancing matrix operation capability while managing buffer memory requirements through targeted rather than universal buffering
Data Source
AI summary
An apparatus to facilitate matrix transposition in matrix multiplication array circuitry is disclosed. The apparatus includes a processor comprising matrix acceleration hardware comprising storage buffers and an array of data processing units (DPUs), wherein the matrix acceleration hardware is to: load data for a source matrix to the storage buffers; generate a transposed matrix corresponding comprising transposed elements of the source matrix; and input the transposed matrix to the array of DPUs for a matrix multiplication operation.