Matrix Transposition in Pipelined Acceleration Units
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Solution Overview
Problem
Conventional matrix transposition methods are difficult to apply in pipelined acceleration unit structures, as they typically require reading from and writing to the same memory, which is not feasible in a pipelined setup where data needs to be shifted across multiple stages.
Innovation Solution
A data processing method that involves reading a row of a target matrix, shifting elements cyclically along a preset offset, and writing them into row buffers, followed by reading from these buffers and combining the elements into an output buffer, allowing for efficient transposition without requiring simultaneous read and write operations in the same memory location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional matrix transposition methods are used (reading from and writing to the same memory), then the transposition operation can be performed, but it cannot be applied in pipelined acceleration unit structures where data needs to be shifted across multiple stages
Solution Approach 1:
The patent introduces intermediate buffers (row buffers and column buffers) as mediators between the input memory and output memory. Data is first read into row buffers, then shifted and transferred to column buffers, and finally written to output memory. This intermediary buffering approach enables the transposition operation to work within pipelined acceleration unit structures by providing separate storage locations for read and write operations across multiple pipeline stages.
2Speed
If data is shifted across multiple pipeline stages, then processing speed is improved, but it becomes difficult to apply conventional matrix transposition methods that rely on simultaneous read and write operations in the same memory
Solution Approach 1:
The patent segments the matrix transposition operation into distinct stages corresponding to different pipeline phases. Each pipeline stage processes a specific portion of the data transformation, with intermediate buffers holding data between stages. This segmentation allows the transposition to be distributed across multiple pipeline stages, enabling high-speed processing while maintaining the transposition functionality.
Solution Approach 2:
The patent transforms the traditional single-memory transposition approach into a multi-dimensional buffer structure with row buffers and column buffers operating in different dimensions of the pipeline. Data flows through these different buffer dimensions in sequence, allowing the transposition operation to adapt to the multi-stage pipeline architecture while maintaining processing efficiency.
3Device complexity
If the same memory is used for both reading and writing during transposition, then memory access is simplified, but simultaneous read and write operations cannot be performed in pipelined acceleration units
Solution Approach 1:
The patent uses intermediate row buffers and column buffers as mediators to separate the read and write memory operations. Input memory writes to row buffers, which then transfer data to column buffers, which finally write to output memory. This intermediary buffering eliminates the conflict of simultaneous read and write operations on the same memory while enabling continuous data flow through the pipeline, thus maintaining high throughput.
Data Source
AI summary
A data processing method and an acceleration unit are provided. The method includes: S11, reading a row of a target matrix as a target row; S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset, and writing each element in the shifted target row into a corresponding row buffer respectively; S13, reading a next row of the target row from the target matrix as a new target row, if the next row of the target row is not the last row of the target matrix and an available storage space exists in the row buffers; S14, reading corresponding elements from each row buffer according to a preset rule, and writing the elements read from each row buffer into an output buffer as a row, step S14 is repeated until all elements in all row buffers are written into the output buffer.