Message Arbitrator Unit for Low-Pin Count USB-C Power Delivery
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Solution Overview
Problem
Existing Power Management Integrated Circuits (PMICs) face challenges in supporting USB Type-C power control due to timing requirements that are difficult to meet using conventional single serial channels, particularly in low-pin count interfaces like I2C, which struggle with low-latency and plug-and-play functionality demands.
Innovation Solution
Implementing a single low-pin count communication link between the host processor and PMIC with a Message Arbitrator Unit (MAU) that employs priority-based message arbitration and delivery, enabling efficient handling of USB-C power delivery timing constraints through multi-priority queues and automatic priority message handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single low-pin count communication link (I2C) is used between host processor and PMIC, then manufacturing cost is reduced and device complexity is lowered, but timing requirements for USB-C power delivery cannot be met and latency increases
Solution Approach 1:
The communication link is segmented into multiple priority queues (first priority queue, second priority queue, third priority queue) within the Message Arbitrator Unit, allowing different types of messages to be transmitted with different priorities. This segmentation enables timely transmission of critical USB-C power delivery messages while maintaining the simplicity of a single physical communication link.
Solution Approach 2:
The Message Arbitrator Unit dynamically adjusts message transmission priority based on the type of message being sent. High-priority messages (such as USB-C power delivery control messages) are automatically given higher transmission priority than low-priority messages (such as status notifications). This dynamic priority adjustment enables the system to meet timing requirements for critical messages while using a single low-pin count link.
2Reliability
If multiple communication interfaces are used to meet USB-C timing requirements, then timing constraints are satisfied and power management efficiency improves, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The single low-pin count communication link is made multi-functional by implementing the Message Arbitrator Unit that handles multiple types of messages with different priorities. The same physical link carries both high-priority USB-C power delivery control messages and low-priority status notifications, eliminating the need for separate dedicated interfaces for each function.
Solution Approach 2:
The Message Arbitrator Unit acts as an intermediary between the host processor and PMIC, mediating the transmission of messages with different priorities through a single communication link. It ensures that timing-critical USB-C power delivery messages receive priority treatment while allowing other messages to be transmitted at lower priorities, thus meeting reliability requirements without adding physical interface complexity.
3Productivity
If priority-based message arbitration is implemented, then guaranteed transmit times for high-priority messages are achieved and power management efficiency improves, but device complexity increases
Solution Approach 1:
The Message Arbitrator Unit implements self-service by automatically determining message priorities and allocating transmission time without requiring external intervention from the host processor or PMIC. The arbitration mechanism autonomously selects which message to transmit next based on predefined priority rules, ensuring guaranteed transmit times for high-priority messages while minimizing the complexity of external control mechanisms.
Data Source
AI summary
Methods and apparatus for implementing a low-pin count architecture with priority message arbitration and delivery. The architecture includes a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, implemented on a first component, such as a processor and/or System on a Chip (SoC). The first component is communicatively coupled to a second component via a low-pin count link such as an I2C bus. The MAU receives prioritized messages from clients and enqueues the messages in priority queues based on their priority levels. An arbiter selects messages to transmit over the low-pin count link from the priority queues. The MAU further may abort transmission of a message in favor of transmission of a higher-priority message to guarantee a transmit latency. Under one implementation, the components are a processor and a PMIC configured to communicate with a USB Type-C power source and meet timing requirements defined by a USB Power Delivery Specification.