Max-Count Address Generator for DRAM Refresh
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Solution Overview
Problem
Dynamic random access memory (DRAM) requires frequent refresh operations due to charge leakage in capacitors, leading to unreliable data storage and potential deterioration of memory cells when frequently accessed row addresses, which increases the complexity of the circuit determining concentrated access addresses.
Innovation Solution
A memory module with max-count address generators in each memory device, which count the number of accesses to row addresses and output max-count address information when a threshold is reached, triggering a buffer unit to refresh corresponding memory cells, thereby reducing circuit complexity and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to maintain data reliability in DRAM, then data integrity is improved, but circuit complexity increases due to the need to determine concentrated access addresses
Solution Approach 1:
The memory device is divided into multiple banks, and each bank is further divided into multiple regions. The max-count address generator is also segmented to count accesses for specific regions rather than the entire memory space. This segmentation allows the refresh circuit to focus only on heavily accessed regions, reducing the overall circuit complexity while maintaining data integrity.
Solution Approach 2:
Instead of applying a uniform refresh strategy across the entire memory, the patent implements localized refresh by identifying specific regions with high access concentrations. The max-count address generator counts accesses region-by-region, and refresh operations are targeted only to those regions exceeding the threshold, thereby reducing unnecessary refresh operations and circuit complexity.
2Measurement precision
If the max-count address generator counts accesses for all regions across all memory devices, then comprehensive monitoring is achieved, but device complexity increases
Solution Approach 1:
The max-count address generator in each memory device is configured to count accesses only for specific regions (e.g., first through third regions) rather than all regions across all memory devices. This segmentation distributes the monitoring task across multiple generators, each handling a subset of regions, thereby reducing individual generator complexity while maintaining comprehensive monitoring coverage.
Solution Approach 2:
The patent introduces a regional dimension to the access counting process. Instead of a single generator handling all regions, multiple generators operate in parallel, each responsible for specific regions. This dimensional distribution of the monitoring function reduces the complexity of each individual generator while achieving comprehensive monitoring accuracy.
Data Source
AI summary
A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.