Maximum Voltage Detection for Delay-Tolerant Power Amplifier Supply

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Solution Overview

Problem

5G-NR mobile communication devices face data throughput reduction due to RF signal propagation attenuation and interference, particularly in the mmWave spectrum, where power amplifiers can clip and distort signals due to misalignment between time-variant voltage and power envelope caused by inherent processing delays in existing power management circuits.

Innovation Solution

A power management circuit with a voltage processing circuit that generates a windowed time-variant target voltage, tolerant of group delays, to ensure proper alignment and prevent amplitude clipping by selecting the highest voltage within defined tolerance windows, thereby maintaining efficient power amplification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a power management circuit uses inherent processing delay in existing designs, then the circuit structure is simpler, but the time-variant voltage becomes misaligned with the power envelope causing amplitude clipping

Engineering Contradiction:
Improvecircuit structureVSAvoidvoltage alignment precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by generating multiple candidate time-variant voltage signals with different group delays before selecting the optimal one. The voltage processing circuit creates several voltage signals that are delayed by different amounts, then selects the signal that best aligns with the power envelope, preventing amplitude clipping while maintaining circuit simplicity.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the power management circuit increases processing speed to reduce delay, then the voltage alignment improves, but the device complexity increases

Engineering Contradiction:
Improvevoltage alignment precisionVSAvoidcircuit structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the voltage generation process into multiple parallel paths, each producing a voltage signal with a different group delay. Instead of using a single complex high-speed processor, the circuit segments the problem into multiple simpler parallel channels that can be easily implemented and selected from.

Inventive Principle:
Principle #1Segmentation

3Productivity

If the power amplifier operates at higher power to overcome propagation attenuation, then data throughput improves, but signal distortion increases due to clipping

Engineering Contradiction:
Improvedata throughputVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies feedback by continuously monitoring the alignment between the time-variant voltage and the power envelope, then adjusting the selection of voltage signals to maintain optimal alignment. This feedback mechanism ensures that the power amplifier operates at high power without causing signal distortion, thereby maintaining both high data throughput and signal quality.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11929713B2Maximum voltage detection in a power management circuit
Publication Date: 2024.03.12 QORVO US INC
  • US11929713B2 patent drawing
  • US11929713B2 patent drawing
  • US11929713B2 patent drawing

AI summary

Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).