μMaxPak Package Architecture for GaN and SiC Power Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power electronic products face challenges in achieving higher circuit and power density, as well as operating at higher frequencies, due to limitations in existing packaging technologies that hinder efficient integration and performance of semiconductor devices.
Innovation Solution
The development of innovative package architectures, such as μMaxPak, which allow for semiconductor devices and components to be assembled in cavities on both sides of leadframes or substrates, enabling exceptional mechanical, thermal, and electrical connections, and accommodating multiple devices with low interconnect inductance and resistance, suitable for high-speed power devices like GaN and SiC switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging technologies are used, then manufacturing simplicity is maintained, but power density and circuit integration are limited
Solution Approach 1:
The patent transitions from traditional two-terminal leadframe packaging to multi-terminal substrate packaging with bottom-side cavities, utilizing the third dimension (vertical depth of cavities) to accommodate multiple semiconductor devices and components. This dimensional change enables higher power density by stacking devices vertically rather than arranging them only in planar configurations.
Solution Approach 2:
The patent implements nesting by placing semiconductor devices, passive components, and interconnect structures within bottom-side cavities of the substrate. Multiple devices are nested within the same package footprint, with components positioned at different depths and levels, effectively utilizing the substrate's internal volume to increase integration density without proportionally increasing package area.
2Speed
If higher operating frequencies are pursued, then performance is improved, but interconnect inductance and resistance become limiting factors
Solution Approach 1:
The patent applies local quality by using different interconnect structures for different signal types and frequency requirements. High-speed signals utilize short, wide, low-inductance paths directly on the substrate, while lower-frequency power connections can use traditional leadframe approaches. This localized optimization of interconnect geometry minimizes inductance and resistance where it matters most for high-frequency operation.
Solution Approach 2:
The substrate itself acts as an intermediary element that provides controlled-impedance transmission lines and low-inductance power distribution networks between semiconductor devices. The substrate's conductive traces and ground planes serve as intermediate interconnect structures that are optimized for high-frequency signal integrity, replacing traditional wire bonds and leadframes that introduce excessive inductance.
3Quantity of substance
If multiple devices are integrated in a single package, then system-in-package complexity increases, but thermal management becomes more challenging
Solution Approach 1:
The patent segments the package into multiple thermal zones with dedicated thermal vias and heat sinks for different device regions. Each semiconductor device has its own thermal path through the substrate to external heat dissipation structures, preventing thermal coupling between adjacent devices. This segmentation allows high-power devices to be integrated closely together while maintaining independent thermal management for each device.
Data Source
AI summary
A new Power DFN and Power QFN package architecture that accommodates Bump-chip die and other components in cavities on the bottom-side of the matrix leadframe, and the technique is also applicable to laminated substrate packages like the BGA and LGA.The package is especially suited for high speed power compound semiconductor devices like GaN and SiC. The package enables single and multiple power switch configurations, and well controlled paralleling of high speed power die switches. It enables co-packaging of associated components like cascoded switchs, gate drivers, isolators and protection devices, which must be tightly coupled at high switching speeds.The architecture accommodates components on the top-side of the leadframe as well allowing for multi-chip functions with extremely low interconnect inductance and resistance, and higher circuit and power densities.The package architecture provides for lower package thermal resistance with parallel thermal paths from both sides of power die to the external bottom-side pads, and supplementary isolated and non-isolated top-side heat dissipation.These type packages use standard proven, reliable and cost effective materials & assembly techniques that are available at commercial contract assemblers. They minimizes NRE for special equipment, tooling and development, and reduces time to market.