Multi-Bridge-Channel Gate Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional multi-gate device structures face challenges with increased parasitic capacitance and reduced switching speed due to dimensional reduction, which are not adequately addressed in existing designs.
Innovation Solution
The implementation of multi-bridge-channel (MBC) transistors with varying gate lengths and pitches, utilizing self-aligned contact (SAC) and non-SAC source/drain contact processes, along with different gate structures and spacer configurations, to optimize performance for high-density, high-voltage, high-frequency, and low-power applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dimensional reduction is implemented in multi-gate devices, then functional density increases, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The device is divided into multiple bridge channels (e.g., four bridge channels) arranged in a bridge configuration, with each channel having its own gate structure. This segmentation allows independent optimization of each channel while reducing overall parasitic capacitance through distributed architecture.
Solution Approach 2:
Different regions of the device have different characteristics: the bridge channels have specific doping profiles, the gate structures have varying lengths and pitches optimized for local performance, and spacer configurations are adjusted locally to control parasitic effects while maintaining high functional density.
2Quantity of substance
If dimensional reduction is implemented in multi-gate devices, then functional density increases, but switching speed decreases
Solution Approach 1:
The channel is segmented into multiple bridge channels with separate gate structures, allowing each segment to switch independently. This reduces the capacitive load on each gate, enabling faster switching speeds while maintaining high functional density through parallel operation of multiple channels.
Solution Approach 2:
The device transitions from a planar 2D channel to a 3D bridge channel structure that extends in multiple dimensions. The bridge channels are arranged vertically and horizontally, creating a multi-dimensional architecture that increases functional density without proportionally increasing parasitic capacitance, thereby preserving switching speed.
3Reliability
If gate structure surrounds channel region completely (MBC transistor), then gate control improves, but device complexity increases
Solution Approach 1:
The surrounding gate structure is divided into multiple discrete gate segments, each controlling a specific bridge channel. This segmentation provides excellent gate control over the channel region while reducing fabrication complexity compared to a fully continuous surrounding gate, as each segment can be formed using standard CMOS processes.
Solution Approach 2:
The gate structures serve multiple functions: they control the channel current, act as electrodes for capacitive coupling, and provide mechanical support for the bridge channel configuration. This multi-functionality reduces the need for additional components, thereby managing device complexity while maintaining superior gate control.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.