Multi-Bridge Channel Gate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional multi-gate device structures face challenges in achieving optimal performance across various applications due to limitations in gate length scaling, parasitic capacitance, and voltage breakdown, which affect the complexity and efficiency of semiconductor integrated circuits.
Innovation Solution
The development of multi-bridge channel (MBC) transistors with varying gate lengths and pitches, utilizing self-align contact (SAC) and non-SAC source/drain contact processes, allows for high-density, high-voltage, high-frequency, and low-power applications by optimizing gate-to-contact spacing and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to improve device scaling and density, then productivity and integration density improve, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The gate structure is segmented into multiple bridges that surround the channel region, creating multiple gate-channel interfaces. This segmentation allows the gate to effectively control the channel from multiple directions, improving gate control without requiring proportional reduction in gate length, thereby managing parasitic capacitance while maintaining scaling benefits.
Solution Approach 2:
The gate structure transitions from a planar configuration to a three-dimensional multi-bridge configuration that surrounds the channel region. This dimensional change allows the gate to control the channel from top, bottom, and sidewalls, effectively increasing gate control without proportionally reducing the horizontal gate length, thus managing parasitic capacitance while maintaining scaling.
2Reliability
If gate structure surrounds channel region to improve gate control, then gate-channel coupling increases, but device complexity increases
Solution Approach 1:
The surrounding gate is segmented into discrete bridge structures rather than forming a continuous enclosure. This segmentation reduces fabrication complexity compared to a fully continuous surrounding gate while still providing multi-directional channel control, balancing gate control improvement with manufacturing feasibility.
Solution Approach 2:
The multi-bridge gate structure serves multiple functions simultaneously: it provides gate control from multiple directions, defines the channel region, and can be integrated with standard planar processing techniques. This multi-functionality reduces the need for additional specialized structures, thereby managing device complexity.
3Productivity
If spacing between gate structures and source/drain contacts is reduced to improve density, then productivity improves, but parasitic capacitance increases
Solution Approach 1:
The gate structure extends vertically and laterally to surround portions of the channel, effectively increasing the gate-controlled volume without proportionally increasing the horizontal footprint. This allows reduced spacing between adjacent devices while the three-dimensional gate configuration manages the parasitic capacitance through improved gate control efficiency.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.