Flexible MBC Sheet Structure for Channel Width PPA Tuning
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Solution Overview
Problem
Existing multi-bridge-channel (MBC) transistors face challenges in achieving optimal performance-power-area (PPA) benefits due to limited flexibility in channel region widths, which affects transistor performance and efficiency in advanced process nodes.
Innovation Solution
Implementing a flexible sheet structure in MBC transistors with varying channel region widths and source/drain feature widths to accommodate different transistor requirements, achieved through layout adjustments and mask data preparation to form photomasks for precise fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed-width channel structure is used in MBC transistors, then the fabrication process is simplified, but the transistor performance and PPA optimization are limited
Solution Approach 1:
The channel structure is divided into multiple segments with different widths (first channel region with first width, second channel region with second width). This segmentation allows each segment to be optimized for different performance requirements while using a unified fabrication process, resolving the contradiction between manufacturing simplicity and performance adaptability.
Solution Approach 2:
Different portions of the channel structure are given different local properties through varying the widths of channel regions. The first channel region has a first width optimized for certain performance characteristics, while the second channel region has a second width optimized for other characteristics, enabling localized performance optimization without complicating the overall fabrication process.
2Manufacturing precision
If uniform channel width is maintained across all MBC transistors, then manufacturing consistency is improved, but performance-power-area optimization is reduced
Solution Approach 1:
The channel structure is segmented into regions with different widths that can be precisely controlled during fabrication. This allows manufacturing precision to be maintained through standardized processes while achieving the variable widths needed for PPA optimization in different channel regions.
Solution Approach 2:
The width parameter of the channel regions is varied between different segments (first width vs. second width) to optimize performance characteristics. This parameter change enables PPA optimization while the fabrication process maintains precision through controlled patterning and etching operations.
3Speed
If channel width is increased to improve current drive, then transistor speed increases, but leakage current increases
Solution Approach 1:
The channel is divided into segments with different widths where wider regions provide high current drive and speed, while narrower regions provide lower leakage. This segmentation allows the transistor to achieve both high speed and low leakage by strategically placing different width regions in the channel structure.
Solution Approach 2:
Different local regions of the channel are optimized for different functions: wider regions are placed where high current drive is needed for speed, while narrower regions are placed where leakage control is critical. This local quality differentiation resolves the contradiction between speed and leakage current.
Data Source
AI summary
Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes channel members vertically stacked above a substrate, a gate structure wrapping around at least one of the channel members, a first epitaxial feature abutting the channel members from a first side of the gate structure, and a second epitaxial feature abutting the channel members from a second side of the gate structure. Between the first and second epitaxial features the channel members have a first width and a second width that is different from the first width in a plan view.