Multi-Bridge Channel Transistor Alignment Keys for Ion Implantation

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Solution Overview

Problem

The manufacturing of multi-bridge channel transistors requires an align key pattern, which is challenging due to the difficulty in distinguishing the step difference between the substrate surface and trenches, leading to alignment issues during the ion implantation process.

Innovation Solution

The formation of first trenches in the scribe lane region with align key patterns having an alternately stacked structure of silicon germanium and silicon patterns, allowing for precise alignment and ion implantation before stacking the silicon germanium and silicon layers, ensuring target compositions and electrical properties of the multi-bridge channel transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional align key patterns are used without stacked structure, then the manufacturing process is simpler, but the alignment precision during ion implantation is insufficient due to difficulty in distinguishing step difference

Engineering Contradiction:
Improvealignment precisionVSAvoidpattern structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The align key pattern is segmented into multiple alternating layers of silicon germanium and silicon materials, creating distinct step differences that enhance visibility and measurement precision during alignment processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The align key pattern uses composite materials (silicon germanium and silicon) with different physical properties to create distinguishable step differences, improving alignment precision without excessive complexity

Inventive Principle:
Principle #40Composite materials

2Reliability

If ion implantation is performed before stacking silicon germanium and silicon layers, then the multi-bridge channel transistor can achieve target electrical properties, but material mixing may occur during the process

Engineering Contradiction:
Improveelectrical propertiesVSAvoidmaterial composition integrity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The ion implantation process is performed as a preliminary action before stacking the silicon germanium and silicon layers, ensuring that the substrate receives necessary doping before the sensitive layered structure is created, thus achieving target electrical properties while preventing material mixing

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the formation of multi-bridge channel transistors with target electrical properties by maintaining the integrity of the silicon germanium and silicon layers, enhancing the alignment precision and reducing the mixing of materials during the ion implantation process.

Implementation Method 1

alternately and repeatedly stacking a silicon germanium layer and a silicon layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

doping impurities into the substrate to form a well region

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS12354899B2Semiconductor devices and methods of manufacturing the same
Publication Date: 2025.07.08 SAMSUNG ELECTRONICS CO LTD
  • US12354899B2 patent drawing
  • US12354899B2 patent drawing
  • US12354899B2 patent drawing

AI summary

A semiconductor device includes a substrate including a main chip region and a scribe lane region, wherein first trenches are formed in the scribe lane region. A well region doped with impurities is provided on an upper part of the main chip region of the substrate. Align key patterns formed on surfaces of the first trenches and on surfaces of the substrate adjacent to the first trenches in the scribe lane region and having an alternately and repeatedly stacked structure of a silicon germanium pattern and a silicon pattern, are provided. A multi-bridge channel transistor is formed on the main chip region of the substrate.