MBC Transistor Channel Stacks for Mixed Drive and Leakage Needs

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Solution Overview

Problem

The semiconductor industry faces challenges in fabricating multi-bridge-channel (MBC) transistors with varying numbers of channel members on the same substrate to meet different application requirements, such as high-power and low-leakage needs, while maintaining similar processes and process windows to reduce costs and improve yield.

Innovation Solution

A method is developed to form MBC transistors with varying numbers of channel members by using a stack of alternating channel and sacrificial layers, patterning fin-shaped structures, and controlling the number of channel layers through etching and dielectric fin formation, allowing for different current driving capabilities in different regions of an IC chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If MBC transistors with varying numbers of channel members are fabricated to meet different application requirements, then adaptability is improved, but device complexity increases

Engineering Contradiction:
ImproveadaptabilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The substrate is divided into multiple regions, with each region containing MBC transistors having a specific number of channel members tailored to different application requirements. This segmentation allows high-power regions to have transistors with more channel members for higher current driving capability, while low-power regions have transistors with fewer channel members for lower leakage, thereby improving adaptability without requiring a completely different device structure across the entire chip.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are assigned different transistor configurations with specific numbers of channel members according to local functional requirements. This local quality approach ensures that each region optimizes its performance characteristics (high current driving capability or low leakage) while maintaining overall device functionality, resolving the contradiction between adaptability and complexity.

Inventive Principle:
Principle #3Local quality

2Power

If different numbers of channel members are used in different regions, then current driving capability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecurrent driving capabilityVSAvoidmanufacturing precision
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The substrate is pre-divided into multiple regions with defined boundaries before transistor fabrication. This preliminary action establishes a framework that guides subsequent processing steps, ensuring that transistors in each region are formed with the correct number of channel members. By preparing the regional structure in advance, the patent reduces the precision requirements during later manufacturing steps compared to forming different transistor types simultaneously across the entire substrate.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240371960A1Nanostructures and method for manufacturing the same
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371960A1 patent drawing
  • US20240371960A1 patent drawing
  • US20240371960A1 patent drawing

AI summary

Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor device includes a first gate structure engaging a plurality of first channel members that are vertically stacked, a first source/drain feature abutting the first channel members, a second gate structure engaging a plurality of second channel members that are vertically stacked, a second source/drain feature abutting the second channel members, a first backside dielectric feature disposed directly under the first gate structure, and a second backside dielectric feature disposed directly under the second gate structure. A number of the first channel members is larger than a number of the second channel members. A top surface of the first backside dielectric feature is below a top surface of the second backside dielectric feature.