MBC Transistor Source/Drain Stress Engineering for Higher Electron Mobility
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Solution Overview
Problem
Existing semiconductor devices, particularly N-type multi-bridge-channel (MBC) transistors, face challenges in achieving enhanced electron mobility, which is crucial for higher switching speed and drive capacity, especially in high-speed wireless and wire-line communication applications.
Innovation Solution
A method involving the formation of a fin-shaped structure with channel layers and sacrificial layers, followed by pre-amorphization implantation, tensile stress film deposition, and annealing to create dislocations in the substrate, enhancing carrier mobility by forming epitaxial source/drain features and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MBC devices continue to scale down, then gate control and short-channel effects are improved, but achieving desired performance (drive capacity and switching speed) becomes more difficult
Solution Approach 1:
The patent changes the physical and chemical parameters of the source/drain region by forming dislocations through pre-amorphization implantation and annealing processes. These dislocations create tensile stress that modifies carrier mobility parameters, enabling higher drive capacity while maintaining the scaled-down geometry for good gate control.
Solution Approach 2:
The patent applies local quality by creating dislocations specifically in the source/drain regions adjacent to the channel, rather than uniformly throughout the device. This localized modification of crystal structure provides enhanced carrier mobility exactly where needed (in the source/drain regions) without affecting the channel dimensions that provide good gate control.
2Reliability
If MBC devices continue to scale down, then gate-channel coupling is improved, but achieving desired performance (switching speed) becomes more difficult
Solution Approach 1:
The patent modifies the carrier mobility parameter in the source/drain regions through dislocation formation, which directly impacts switching speed. The pre-amorphization implantation followed by annealing creates dislocations that generate tensile stress, changing the physical parameters of the source/drain region to enable faster carrier injection and extraction, thereby improving switching speed while maintaining good gate-channel coupling.
3Reliability
If pre-amorphization implantation and annealing are performed, then carrier mobility is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing pre-amorphization implantation before the main epitaxial growth process. This preliminary modification of the substrate crystal structure prepares the source/drain regions to develop dislocations during subsequent annealing, achieving carrier mobility enhancement as an integrated part of the fabrication sequence rather than as a separate post-processing step.
4Reliability
If dislocations are formed in the substrate, then electron mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-service by utilizing the natural tendency of dislocations to form during the annealing of pre-amorphized regions. The process leverages the material's own phase transformation behavior (from amorphous to crystalline) to generate dislocations automatically, rather than requiring precise external control or intervention to create them. This reduces manufacturing precision requirements while still achieving the desired electron mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electron mobility in N-type MBC transistors, leading to increased drive capacity and switching speed without significant additional manufacturing costs or complexity.
Implementation Method 1
performing a pre-amorphization implantation (PAI) process to amorphize a portion of the substrate exposed by the source/drain opening
Implementation Method 2
performing an annealing process to recrystallize the amorphized portion of the substrate. The recrystallized portion of the substrate includes dislocations
Implementation Method 3
forming a tensile stress film over the substrate, performing an annealing process to recrystallize the amorphized portion of the substrate
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a PAI process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. By performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.