MBCFET Gate Structure With Air Gaps for Threshold Voltage Control
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and three-dimensional channel structures to overcome limitations in operating characteristics due to size reductions in planar metal oxide semiconductor FETs.
Innovation Solution
A semiconductor device with a multi-bridge channel FET (MBCFET) structure featuring a gate-all-around field effect transistor, including a substrate with active regions, gate electrodes, channel layers, source/drain regions, and air gap regions, where the gate electrode layers have varying thicknesses to optimize electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor FETs are reduced in size to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional vertical channel structure. The channel extends vertically through multiple layers with gate electrodes positioned at different heights, creating a 3D configuration that maintains effective channel length while reducing footprint area, thereby improving integration density without sacrificing operating characteristics.
Solution Approach 2:
The patent implements nested gate electrodes where a first gate electrode and a second gate electrode are positioned at different vertical levels, with the second gate electrode partially surrounding or nested within the structure defined by the first gate electrode. This nested configuration allows multiple gating functions within a compact vertical space, maintaining device performance while enabling higher integration.
2Productivity
If fine patterns are implemented to increase integration, then device density improves, but manufacturing complexity increases
Solution Approach 1:
The gate electrode structure is segmented into multiple distinct components: a first gate electrode and a second gate electrode positioned at different vertical levels. This segmentation allows each gate electrode to be formed and controlled independently through separate processing steps, simplifying the fabrication of the overall fine-pitch structure by breaking down the complex 3D pattern into manageable segments.
Solution Approach 2:
By moving from 2D planar patterning to 3D vertical patterning, the patent reduces the lateral pitch requirements. The vertical stacking of channel layers and gate electrodes allows integration density to increase in the vertical dimension rather than requiring proportionally finer lateral patterning, thereby reducing manufacturing complexity associated with ultra-fine lateral features.
3Reliability
If three-dimensional channel structures are used to improve operating characteristics, then device performance improves, but device complexity increases
Solution Approach 1:
The patent employs nested gate electrodes where the second gate electrode is positioned within the vertical space defined by the first gate electrode structure. This nesting allows the complex 3D channel to be controlled by multiple gates in a compact configuration, improving operating characteristics through enhanced electrostatic control while keeping the overall device footprint and structural complexity manageable.
Solution Approach 2:
Different regions of the channel structure receive different gating control: the first gate electrode controls certain vertical regions while the second gate electrode controls other vertical regions. This local differentiation of gating quality allows optimization of operating characteristics in different parts of the 3D channel, improving overall device performance while maintaining a systematic structure that doesn't excessively increase complexity.
Data Source
AI summary
A semiconductor device includes: a substrate including an active region extending in a first direction; a gate electrode extending in a second direction and intersecting the active region, the gate electrode including first electrode layer(s) and a second electrode layer;, channel layers spaced apart from each other in a third direction and at least partially surrounded by the gate electrode; source/drain regions, with at least one source/drain region on each side of the gate electrode and electrically connected to the channel layers; and air gap regions in the second electrode layer between the channel layers and between a lowermost channel layer and the active region in the third direction. The first electrode layer(s) or the second electrode layer has a first thickness between adjacent ones of the channel layers in the third direction, and has a second thickness greater than the first thickness on side surfaces of the channel layers.