MBCFET Gate Structure With Asymmetric Overlap for Stable Scaling
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Solution Overview
Problem
As semiconductor devices become highly integrated, it is challenging to meet the performance demands of transistors due to decreasing gate and channel lengths, requiring improved manufacturing processes and structures to enhance operation stability and reliability.
Innovation Solution
The semiconductor device design includes specific active patterns and gate electrodes with varying depths and orientations to improve transistor performance and reliability, featuring a first active pattern with a first lower pattern and first sheet pattern, and a second active pattern with a second lower pattern and second sheet pattern, where the gate electrodes overlap the sidewalls of the lower patterns by different depths, optimizing the gate insulating layer and gate electrodes' positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length and channel length are decreased to increase integration density, then device integration is improved, but transistor performance and operation stability deteriorate
Solution Approach 1:
The gate electrode is configured to surround the sheet pattern in a bridge-channel structure, with the gate insulating layer nested between them. This nested arrangement creates multiple gate-to-channel interfaces within a compact footprint, effectively increasing the functional gate area without proportionally increasing the device footprint, thus maintaining performance at reduced dimensions
Solution Approach 2:
The invention transitions from a planar gate-to-channel interface to a three-dimensional surrounding interface where the gate electrode envelops the sheet pattern. This dimensional change increases the effective gate area and control capability without increasing the lateral footprint, enabling better performance at reduced gate lengths
2Reliability
If gate electrode depth is increased to improve gate control, then transistor performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate electrode is designed with asymmetric depth characteristics - deeper on one side and shallower on the other - allowing optimization of gate control in critical regions while reducing complexity and parasitic effects in less critical regions. This asymmetric configuration enables tailored performance without requiring uniform deep gates throughout
Solution Approach 2:
Different portions of the gate electrode structure have different depths and configurations optimized for their specific functions. The gate electrode surrounding the sheet pattern has varying depth to provide enhanced control where needed while maintaining simpler structure elsewhere, reducing overall device complexity
Data Source
AI summary
Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.