3D MBCFET Channel Structure for Short-Channel Current Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in improving element performance and reliability, particularly in scaling techniques that require effective current control and suppression of short channel effects.
Innovation Solution
The semiconductor device incorporates a multi-bridge channel field effect transistor (MBCFET) design with specific structural features, including multiple active patterns and gate structures, to enhance performance and reliability. This design includes a first substrate with multiple interlayer insulating layers, active patterns with varying heights, and gate structures with different widths to optimize current control and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor with three-dimensional channel is used, then current control capability is improved, but device complexity increases
Solution Approach 1:
The channel is divided into multiple segments (first channel, second channel, third channel) with different gate structures (first gate, second gate, third gate). Each segment can be independently controlled, allowing precise current control while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent transitions from planar two-dimensional channel to three-dimensional multi-bridge channel structure. The channel extends in multiple dimensions with gates positioned at different heights and locations, enabling superior current control through enhanced electric field modulation in three-dimensional space
2Productivity
If pitch size is reduced, then device density is improved, but electrical stability between contacts deteriorates
Solution Approach 1:
The patent utilizes three-dimensional channel structure and multi-level gate positioning to achieve high device density without compromising contact stability. By extending the channel in multiple dimensions rather than simply reducing planar pitch, electrical stability is maintained while improving overall device density
Solution Approach 2:
Different regions of the device have optimized local characteristics - the channel regions have specific doping profiles and geometries for stability, while the gate structures have varying widths and positions for density optimization. This local optimization allows simultaneous achievement of high density and electrical stability
3Reliability
If gate length is increased, then current control capability is improved, but short channel effect suppression deteriorates
Solution Approach 1:
The channel is segmented into multiple sections controlled by different gates. This segmentation allows effective current control through coordinated gate operation while each segment maintains dimensions that suppress short channel effects, preventing the need for excessive overall gate length
Solution Approach 2:
The patent employs three-dimensional channel structure with gates positioned at different heights and locations. This multi-dimensional configuration provides effective current control and electrostatic control to suppress short channel effects without requiring increased gate length in a single dimension
Data Source
AI summary
A semiconductor device includes a first substrate having a first surface and a second opposite surface, a first lower interlayer insulating layer on the second surface, a first active pattern including a first lower pattern contacting the first surface, a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction, a first gate structure on the first lower pattern, a first source/drain pattern on a side of the first gate structure, a second lower interlayer insulating layer including a third surface and a fourth opposite surface, a second active pattern including a second lower pattern contacting the third surface, a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction, a second gate structure on the second lower pattern, wherein the first lower pattern has a first height, and the second lower pattern has a second different height.