MBCFET Channel Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and three-dimensional channel structures to overcome the limitations of planar metal oxide semiconductor FETs, particularly in reducing parasitic capacitance to improve AC performance and power characteristics.
Innovation Solution
A semiconductor device with a Multi-Bridge-Channel FET (MBCFET) structure featuring a gate-all-around type field effect transistor, including a substrate with active regions, channel layers, gate structures, and source/drain regions, where the uppermost channel layer is designed with channel portions separated to minimize parasitic capacitance by being positioned below the gate spacer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFETs with three-dimensional channel structure are used to reduce operating limitations, then device performance is improved, but parasitic capacitance increases
Solution Approach 1:
The channel layer is divided into multiple segments along the channel length direction, creating multiple channel regions separated by insulating layers. This segmentation reduces the continuous channel structure that generates parasitic capacitance, while maintaining the three-dimensional gate control benefits of FinFET architecture.
Solution Approach 2:
The patent implements a multi-layer channel structure where channel layers are nested vertically with insulating layers between them. The gate electrode surrounds these nested channel structures, providing gate-all-around control. This nested configuration reduces parasitic capacitance by breaking up the continuous channel while preserving effective gate control.
2Speed
If channel layers are separated to reduce parasitic capacitance, then AC performance is improved, but device complexity increases
Solution Approach 1:
The channel is segmented into multiple discrete layers separated by insulating materials, which reduces parasitic capacitance and improves AC performance. The segmentation is achieved through a systematic stacking approach that, while adding structural elements, does so in a regular pattern that can be manufactured using standard semiconductor processes.
Solution Approach 2:
The patent transitions from a planar channel structure to a vertical multi-layer channel structure. By stacking channel layers in the vertical dimension with insulating layers between them, the design reduces parasitic capacitance in the horizontal plane while utilizing the vertical dimension for structural organization. This dimensional transition improves AC performance without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode layer crossing the active region and extending in a second direction, a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region, and surrounded by the gate electrode layer, gate spacer layers disposed on side surfaces of the gate electrode layer in the first direction, and source/drain regions disposed on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers. An uppermost channel layer among the plurality of channel layers includes channel portions separated from each other in the first direction and disposed below the gate spacer layers.