MBCFET Source/Drain Contact Layout for Stable Current Flow

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving high integration and electrical stability as device sizes decrease, particularly in maintaining efficient current flow and capacitance in multi-bridge channel field effect transistors (MBCFETs).

Innovation Solution

The semiconductor device design includes extending at least a part of the source/drain contact into the element isolation region within a MBCFET structure, utilizing fin-shaped patterns, nanowires, and gate electrodes to improve current flow and electrical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor devices are scaled down in size for high integration, then device density and cost-effectiveness are improved, but electrical stability and current flow efficiency deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidelectrical stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain contact is extended from a purely planar configuration into the vertical dimension by projecting it into the element isolation region. This three-dimensional contact structure increases the effective contact area and improves electrical stability without increasing the planar footprint of the device, thereby maintaining high integration density while enhancing reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source/drain contact is formed to extend into the element isolation region before final device assembly. This preliminary extension ensures optimal electrical connection and stability is established early in the fabrication process, preventing subsequent electrical issues without requiring additional processing steps that would increase device complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If source/drain contact area is increased to improve current flow, then electrical performance is improved, but device area and integration density worsen

Engineering Contradiction:
Improvecurrent flow efficiencyVSAvoiddevice footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing the planar area of the source/drain contact, the contact is extended vertically into the element isolation region. This dimensional transition allows the contact to achieve larger effective area for improved current flow while maintaining a compact planar footprint, thus improving electrical performance without sacrificing integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If element isolation regions are used to separate devices, then device stability and electrical isolation are improved, but available active area and integration density worsen

Engineering Contradiction:
Improveelectrical isolationVSAvoidintegration density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The source/drain contact structure merges with the element isolation region by extending into it, creating a combined structure that serves dual purposes: maintaining electrical isolation between devices while providing enhanced current flow pathways. This merging eliminates the need for separate isolation structures, thereby improving electrical isolation without reducing integration density.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12142650B2Semiconductor device
Publication Date: 2024.11.12 SAMSUNG ELECTRONICS CO LTD
  • US12142650B2 patent drawing
  • US12142650B2 patent drawing
  • US12142650B2 patent drawing

AI summary

A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.