3D MBCFET Gate-Contact Structure for Scaled MOSFET Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electric characteristics for high-performance semiconductor devices.
Innovation Solution
A semiconductor device with a multi-bridge channel field-effect transistor (MBCFET) design, featuring three-dimensional gate electrodes surrounding channel patterns, and a structure with epitaxial source/drain patterns and specific gate insulating layers, including ferroelectric and paraelectric materials, to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from conventional planar MOS-FET structures to three-dimensional multi-bridge channel FET structures. The gate electrode extends in multiple directions (first direction crossing channel, second direction parallel to channel) creating a multi-dimensional gate configuration that surrounds the channel pattern, thereby improving operational properties without further scaling down the pattern size.
Solution Approach 2:
The gate electrode is configured to surround the channel pattern in a nested arrangement, with the gate wrapping around the channel in multiple directions. This nested structure increases the effective gate control over the channel without increasing the overall device footprint, addressing the deterioration of operational properties while maintaining compact dimensions.
2Adaptability or versatility
If additional conductive vias are used to connect gate electrodes and active contacts to interconnection lines, then connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the gate electrode and active contact structures by configuring them to be in direct contact with the same lower interconnection line. This integration eliminates the need for separate additional conductive vias that would otherwise be required to connect these elements to interconnection lines, thereby reducing device complexity while maintaining improved connectivity.
Solution Approach 2:
The lower interconnection line serves multiple functions by being in direct contact with both the gate electrode and active contact. This multi-functional connection approach eliminates the need for dedicated separate connection structures, reducing overall device complexity while achieving versatile connectivity for both gate control and active contact functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves operational characteristics by reducing subthreshold swing and enhancing integration density while minimizing process defects and misalignment issues, thereby supporting high-performance semiconductor device operation.
Implementation Method 1
a first gate insulating layer GI1 including a ferroelectric layer FE
Implementation Method 2
a second gate insulating layer GI2 including a paraelectric layer PE
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A semiconductor device (LC) may include an active pattern (AP1, AP2) on a substrate (100), a source/drain pattern (SD1, SD2) on the active pattern, a channel pattern (CH1, CH2) connected to the source/drain pattern, a gate electrode (GE) on the channel pattern, an active contact (AC) on the source/drain pattern, a first lower interconnection line (M1_I4) on the gate electrode, and a second lower interconnection line (M1_I1) on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion (GB) and an electrode protruding portion (GC), wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion (LB) and a contact protruding portion (LA), wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.