MBCFET Gate Isolation Structure for Connectivity Defect Reduction
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Solution Overview
Problem
Existing semiconductor devices, particularly multi-bridge channel field effect transistors (MBCFETs), face constraints in achieving optimal electrical characteristics due to electrical connectivity issues between gate structures.
Innovation Solution
The semiconductor device incorporates a unique design with active structures, isolation patterns, gate structures, and cutting insulation patterns, where the lower impurity region contacts the cutting insulation pattern, and the shapes of the lower portions of the cutting insulation and gate structures differ, reducing electrical connectivity defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structures are formed to extend across the active structures, then the electrical characteristics are improved, but electrical connectivity defects between gate structures occur
Solution Approach 1:
The gate structure is segmented into multiple parts: the first gate structure on the first active structure, the second gate structure on the second active structure, and the third gate structure on the isolation pattern between them. This segmentation prevents direct electrical connection between adjacent gate structures while maintaining individual functionality, thereby resolving the connectivity defect issue while preserving electrical characteristics.
Solution Approach 2:
The third gate structure formed on the isolation pattern acts as an intermediary element between the first and second gate structures. This intermediate structure provides electrical isolation and prevents unwanted connectivity between adjacent gate structures, while the overall gate system continues to provide the necessary electrical characteristics for device operation.
2Reliability
If the cutting insulation pattern extends to the upper portion of the isolation pattern, then the electrical isolation is improved, but the device complexity increases
Solution Approach 1:
The third gate structure is formed by merging the cutting insulation pattern with the gate electrode structure. The cutting insulation pattern that extends to the upper portion of the isolation pattern is integrated into the gate structure formation process, creating a unified structure that provides both electrical isolation and gate functionality without requiring separate complex components.
Solution Approach 2:
The third gate structure on the isolation pattern serves multiple functions simultaneously: it provides electrical isolation between adjacent gate structures, maintains the electrical characteristics of the device, and acts as part of the overall gate system. This multi-functionality reduces the need for additional separate structures, thereby managing complexity while achieving improved isolation.
Data Source
AI summary
The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.