MBCFET Gate Overlap Asymmetry for Stable High-Density Scaling
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Solution Overview
Problem
As semiconductor devices become highly integrated, it becomes increasingly difficult to meet transistor performance demands due to the challenges of reducing gate and channel lengths while maintaining operation stability and reliability.
Innovation Solution
The semiconductor device incorporates a Multi-Bridge Channel Field Effect Transistor (MBCFET) design with specific active patterns and gate electrodes configurations, including asymmetrical overlap depths of gate electrodes over the active pattern sidewalls, to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length and channel length are reduced to increase integration density, then device integration is improved, but operation stability and reliability deteriorate
Solution Approach 1:
The patent introduces a multi-bridge channel structure where gate electrodes extend in multiple directions (first direction along channel, second direction bridging between channels) to create a three-dimensional configuration. This dimensional change allows the gate to control multiple channels simultaneously without reducing individual channel lengths, thereby maintaining reliability while improving integration density.
Solution Approach 2:
The patent implements a nested structure where sheet patterns are positioned between lower patterns, and gate electrodes surround these nested elements. The multi-bridge channel structure nests multiple channels within a compact footprint, allowing higher integration density without compromising the operational characteristics of individual channels.
2Productivity
If gate length is reduced to increase integration, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the gate structure into multiple segments - lower patterns, sheet patterns, and gate electrodes - that can be formed and controlled independently. The asymmetric overlap depths of gate electrodes on opposite sidewalls allow for independent optimization of each segment's dimensions, reducing the cumulative precision requirements compared to a single continuous gate structure.
Solution Approach 2:
The patent employs asymmetric overlap depths where gate electrodes overlap opposite sidewalls of lower patterns by different depths. This asymmetric design provides manufacturing flexibility, allowing optimization of critical dimensions for each side independently, thereby reducing the overall manufacturing precision requirements while maintaining device performance.
Data Source
AI summary
Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.