MBCFET Gate Structure With Stepped Length to Cut Parasitic Capacitance
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Solution Overview
Problem
Multi-bridge-channel metal-oxide-semiconductor field-effect transistors (MBCFETs) face challenges in reducing parasitic capacitance between the gate structure and the source/drain layer, which affects the electrical characteristics of vertically stacked channel semiconductor devices.
Innovation Solution
The semiconductor device design includes a gate structure with a varying length in the vertical direction, featuring an upper portion with a longer length and a lower portion with a shorter length, and the use of spacers with a horseshoe shape convex toward the central portion of the gate structure, which reduces parasitic capacitance by creating an air gap and optimizing spacer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure length is increased to improve current drivability, then the electrical characteristics are improved, but the parasitic capacitance between the gate structure and source/drain layer increases
Solution Approach 1:
The gate structure is divided into multiple segments with different lengths in the vertical direction. The upper portion has a longer length extending closer to the source/drain layer, while the lower portion has a shorter length, creating a stepped configuration that reduces parasitic capacitance while maintaining current drivability
Solution Approach 2:
Different portions of the gate structure are given different lengths to optimize local electrical characteristics. The upper portion near the source/drain layer has a longer length to control parasitic capacitance, while the lower portion has a shorter length to maintain current flow, creating locally optimized electrical properties throughout the structure
2Object-affected harmful factors
If spacers are added to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the device structure becomes more complex
Solution Approach 1:
The spacers are designed with a horseshoe shape that is convex toward the central portion of the gate structure, creating a curved configuration that efficiently reduces parasitic capacitance while integrating smoothly with the overall device geometry
Solution Approach 2:
Spacers are introduced as intermediary elements positioned between the gate structure and source/drain layer. These spacers act as mediators that electrically isolate the gate from the source/drain region, reducing parasitic capacitance without requiring direct modification of the primary functional components
Data Source
AI summary
A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.