MBCFET Channel Structure With SiGe Stress for PMOS and NMOS
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Solution Overview
Problem
The challenge lies in developing processes for forming multi-bridge-channel MOSFETs (MBCFETs) with vertically stacked channels in PMOS and NMOS regions, where charges in the PMOS region require enhanced mobility and channels in the NMOS region need to be longer.
Innovation Solution
A semiconductor device is designed with an active pattern on a substrate, featuring a gate structure crossing the active pattern, channels spaced apart perpendicular to the substrate, and source/drain layers contacting the channels. The device includes a sacrificial pattern with silicon-germanium on opposite edges of the source/drain layer, optimizing channel characteristics for both PMOS and NMOS regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-bridge-channel MOSFET is formed with vertically stacked channels, then the device can achieve higher integration density, but the process complexity increases and different regions require different channel characteristics
Solution Approach 1:
The device is divided into separate PMOS and NMOS regions, each with independently optimized channel structures. The PMOS region has channels with enhanced mobility characteristics while the NMOS region has channels with longer length, allowing each segment to be tailored for its specific function while maintaining overall integration density
Solution Approach 2:
Different channel characteristics are implemented in different spatial locations within the device. The PMOS region employs channels with properties optimized for charge mobility, while the NMOS region uses channels with properties optimized for length, creating local quality variations that resolve the contradiction between integration density and process complexity
2Speed
If channels in the PMOS region are designed for enhanced mobility, then charge transport efficiency improves, but the channel structure becomes more complex to fabricate
Solution Approach 1:
The PMOS region channels are given special local quality characteristics including adjusted composition and structure to enhance charge mobility. This localized optimization allows high-speed performance in the PMOS region without requiring the entire device structure to be complex
3Manufacturing precision
If channels in the NMOS region are made longer, then the channel length control precision improves, but the overall device area increases
Solution Approach 1:
The channel structure transitions from a planar two-dimensional layout to a three-dimensional vertically stacked configuration. This dimensional change allows the NMOS channels to achieve longer effective lengths through vertical stacking rather than horizontal extension, improving channel length control precision while minimizing the increase in device footprint area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves enhanced charge mobility in PMOS regions due to the compressive stress from the source/drain layer and maintains long, constant-length channels in NMOS regions, thereby improving the overall electric characteristics of the transistors.
Implementation Method 1
the source/drain layer contacting the channels... achieves enhanced charge mobility in PMOS regions due to the compressive stress from the source/drain layer
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.