Processor Storage Layout Using MBFFs for High-Toggle Bits
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Solution Overview
Problem
Flip flops in processor circuits consume significant energy due to frequent state changes, particularly in intense data calculation processors like artificial intelligence processors.
Innovation Solution
Implementing a data storage module with a combination of multibit flip flop circuits (MBFF) and single bit flip flop circuits (SBFF), where MBFFs with lower power consumption per bit are used for data bits that toggle more frequently and SBFFs with higher power consumption are used for data bits that toggle less frequently, optimizing power usage across the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional single bit flip flop circuits are used to store all data bits, then the processor can handle frequent state changes, but the power consumption increases significantly
Solution Approach 1:
The patent segments the data storage functionality by dividing flip flop circuits into two distinct types: single-bit flip flops for frequently changing bits and multi-bit flip flops for less frequently changing bits. This segmentation allows each type to be optimized for its specific usage pattern, reducing overall power consumption while maintaining the processor's ability to handle frequent state changes.
Solution Approach 2:
The patent applies local quality by assigning different characteristics to different parts of the data storage system. Specifically, single-bit flip flops with higher power consumption are allocated to bits that change frequently, while multi-bit flip flops with lower power consumption are allocated to bits that change less frequently. This localized optimization ensures that power consumption is minimized without compromising the processor's overall functionality.
2Use of energy by moving object
If multi bit flip flop circuits are used to reduce power consumption per bit, then power efficiency improves, but the ability to quickly handle frequent state changes may be compromised
Solution Approach 1:
The patent segments the flip flop population into single-bit and multi-bit types, each optimized for different performance characteristics. Single-bit flip flops provide fast response for frequently changing bits, while multi-bit flip flops provide power efficiency for stable bits. This segmentation resolves the contradiction by ensuring that speed requirements are met for bits that need it, while power efficiency is achieved for bits that don't require frequent changes.
Solution Approach 2:
The patent applies local quality by matching the characteristics of individual flip flops to the specific requirements of the bits they store. Bits that require fast state changes are assigned to single-bit flip flops with optimized speed characteristics, while bits that are more stable are assigned to multi-bit flip flops with optimized power consumption characteristics. This localized matching ensures that speed is not compromised where needed while achieving power efficiency where possible.
3Speed
If all flip flops are designed for high speed operation, then processing speed is maximized, but power consumption increases
Solution Approach 1:
The patent segments the flip flop design into two categories with different speed-power tradeoffs. Single-bit flip flops are designed for high speed operation to handle frequently changing data, while multi-bit flip flops are designed for lower power consumption to handle more stable data. This segmentation allows the processor to achieve high processing speed where necessary while minimizing overall power consumption.
Solution Approach 2:
The patent applies local quality by assigning different speed characteristics to different flip flops based on the specific requirements of the bits they store. Critical bits that require fast processing are handled by high-speed single-bit flip flops, while non-critical bits are handled by power-efficient multi-bit flip flops. This localized optimization ensures that processing speed is maximized for essential operations while reducing power consumption for less critical operations.
Data Source
AI summary
Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.