MBIST Controller Address Permutation for Multi-Organization Memory Testing
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Solution Overview
Problem
Existing built-in self-test (BIST) controllers for memory arrays on integrated circuits face challenges in efficiently testing memory arrays with different physical organizations, often requiring significant logic and die area, or failing to exercise fault modes dependent on physical organization.
Innovation Solution
A single memory BIST controller is configured to generate logical addresses that are permuted to produce physical addresses, taking into account the physical organization of each memory array, using a state machine, address generator, data generator, read/write control generator, and comparator to conduct tests like fast row, fast column, and fast bank tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate memory BIST controller is implemented for each memory array or different types of memory arrays, then the testing effectiveness for each array's physical organization is improved, but the die area requirement increases prohibitively
Solution Approach 1:
The patent implements a single universal BIST controller that can test multiple different types of memory arrays with different physical organizations. The controller includes a configurable address generator that can be programmed with different address permutation patterns to accommodate various memory organizations (e.g., row-major, column-major, interleaved). This multi-functional approach eliminates the need for separate dedicated controllers for each memory array type, significantly reducing die area while maintaining comprehensive testing capability across all array types.
Solution Approach 2:
The BIST controller employs dynamic reconfiguration capability through programmable address generators and configurable control logic. The controller can adapt its behavior and address generation patterns dynamically based on the specific memory array being tested. This dynamic adaptability allows a single controller to effectively become specialized for different memory organizations during different test sequences, achieving the reliability of dedicated controllers without their area overhead.
2Reliability
If a single memory BIST controller with logic to account for each type of array is implemented, then testing coverage for different physical organizations is improved, but the device complexity increases
Solution Approach 1:
The BIST controller is segmented into distinct functional modules: an address generator unit, a data pattern generator unit, a control state machine, and a comparator unit. The address generator is further segmented into configurable components that can be independently programmed. This modular segmentation reduces overall complexity by allowing each module to be designed and verified independently, while maintaining the ability to handle multiple memory array types through coordinated operation of the segments.
Solution Approach 2:
The patent introduces a configuration interface and control state machine as intermediary components between the simple address generator and the diverse memory array types. This intermediary layer translates high-level test requirements into array-specific address sequences through programmable address permutation logic. The intermediary absorbs the complexity of handling different memory organizations, allowing the core testing functionality to remain relatively simple while achieving comprehensive coverage.
3Area of stationary object
If a smaller single memory BIST controller using logical addresses is implemented, then the die area is reduced, but the ability to exercise fault modes dependent on physical organization is lost
Solution Approach 1:
The patent changes the parameters of the address generator from fixed logical address generation to programmable address generation with configurable permutation patterns. By making the address generation parameters configurable, the controller can transform logical address sequences into physical address sequences that respect the specific physical organization of any memory array type. This parameter change enables the small-area controller to maintain full fault mode exercise capability across different memory organizations.
Solution Approach 2:
The controller performs preliminary configuration of the address generator with the appropriate address permutation pattern before initiating a test sequence on a specific memory array type. This preliminary action programs the controller with the necessary knowledge of the target array's physical organization, enabling it to generate physically meaningful address sequences without requiring complex real-time decision logic during the actual test execution. This advance preparation maintains fault coverage while keeping the running controller simple.
Data Source
AI summary
An integrated circuit (IC) having a memory built-in self-test (MBIST) controller. The IC includes an MBIST controller and a plurality of memory arrays. One or more the memory arrays has a different physical organization with respect to other ones of the memory arrays. The MBIST controller is configured to generate a logical address of a memory under test. The MBIST controller is further configured to permute the bits to produce a physical address. The user programmed permutation enables a simple address incrementer to create an address sequence that traverses the physical organization of the memory in accordance with the type of desired test.