Configurable MBIST Circuit Generation via Editable Test Files

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Solution Overview

Problem

Conventional memory built-in self-test (MBIST) systems are inflexible and limited in customizability, requiring hardware connections for each test pattern and lacking the ability to combine multiple test algorithms, leading to increased testing time and cost due to repeated testing for error detection.

Innovation Solution

A method for generating a customizable MBIST circuit through an editable file that allows users to edit memory test algorithms, with syntax parsing to obtain memory test data including address, address mask, and pattern data, enabling the generation of a tailored MBIST circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If hardware-controlled logic circuits are used to generate test patterns, then test pattern generation is achieved, but the system cannot be reprogrammed or redesigned for different test patterns after fabrication

Engineering Contradiction:
Improvetest pattern customizabilityVSAvoidhardware connection complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent uses a file-based configuration (copyable text data) to represent test pattern specifications instead of hardwiring each pattern. The configuration file contains address data, address mask data, and pattern data that define test behavior, allowing easy replication and modification of test patterns without changing hardware connections.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent enables dynamic parameter changes by allowing users to modify test pattern parameters (address ranges, patterns, masks) in the configuration file after fabrication. This changes the behavioral parameters of the MBIST controller without requiring physical hardware reconfiguration, resolving the contradiction between adaptability and hardware complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple test algorithms are combined to avoid detection failure, then error detection capability is improved, but testing time increases due to repeated testing

Engineering Contradiction:
Improveerror detection capabilityVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple test algorithm specifications into a single configuration file that defines address data, address mask data, and pattern data collectively. This allows the MBIST controller to execute a comprehensive test sequence that covers multiple error detection scenarios in one unified test run, rather than running separate repeated tests.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic test sequence generation where the controller adapts the test execution flow based on the configuration file specifications. The system dynamically selects and combines test patterns based on address ranges and masks defined in the file, optimizing the test sequence to achieve comprehensive coverage without redundant repeated testing.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If existing MBIST systems are used with limited test algorithms, then system simplicity is maintained, but user customization capability is restricted

Engineering Contradiction:
Improvetest algorithm customizationVSAvoidsystem implementation complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent introduces a configuration file as an intermediary layer between the user and the MBIST controller hardware. This file serves as a mediator that translates user customization requirements into controller-executable instructions, enabling full customization capability without complicating the actual hardware manufacturing or controller design.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11776649B2Method for generating an memory built-in self-test algorithm circuit
Publication Date: 2023.10.03 ISTART TEK INC
  • US11776649B2 patent drawing
  • US11776649B2 patent drawing
  • US11776649B2 patent drawing

AI summary

A method for generating a memory built-in self-test circuit includes steps of providing an editable file, wherein the editable file configured to be edited by a user to customize a memory test algorithm; performing a syntax parsing on the editable file to obtain the memory test data, wherein the memory test data being corresponding to the memory test algorithm; and generating the memory built-in self-test circuit based on the memory test data.