MBIST Control Circuitry for Concurrent Memory Testing
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Solution Overview
Problem
Existing online memory built-in self-test (MBIST) techniques significantly impact the regular functioning of processing circuitry, as they often require interrupting processor operations to perform memory tests, which is undesirable for safety-critical systems.
Innovation Solution
The implementation of control circuitry that reserves specific memory locations for testing without interrupting processor operations, allowing the processor to continue normal functionality by reserving only a portion of memory for testing and using existing memory control circuitry to manage transactions, thereby minimizing performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing online MBIST techniques are used to test memory, then memory testing can be performed, but the regular functioning of processing circuitry is significantly impacted
Solution Approach 1:
The memory system is divided into tested memory locations and untested memory locations. The control circuitry segments the memory address space by setting bits in the lock register corresponding to tested locations, allowing the processor to access only untested portions during normal operation while testing occurs in parallel on segmented portions.
Solution Approach 2:
A lock register acts as an intermediary between the MBIST interface and the memory array. This intermediary component receives test enable signals, generates lock signals to prevent processor access to tested locations, and provides arbitration between test transactions and regular memory transactions, thereby mediating the conflict between testing and normal operation.
2Reliability
If software is used to perform MBIST by stopping normal operation and entering test mode, then comprehensive memory testing can be conducted, but the processor cannot carry out its normal functionality
Solution Approach 1:
The system enables continuous operation by allowing the processor to continue accessing untested memory locations while MBIST testing proceeds in parallel on tested locations. The lock register mechanism ensures that tested locations are temporarily inaccessible only during their specific test windows, while other memory regions remain fully accessible, maintaining continuous useful action throughout the system.
Solution Approach 2:
Memory testing is performed periodically on specific memory locations rather than requiring a complete system stop. The MBIST interface can initiate periodic test transactions on locked locations while the processor continues normal operations on unlocked locations, creating a periodic testing rhythm that does not interrupt overall system functionality.
3Adaptability or versatility
If dedicated control circuitry is provided to reserve memory locations for testing, then MBIST can coexist with regular functions, but device complexity increases
Solution Approach 1:
The lock register and control circuitry serve multiple functions: they manage memory access arbitration between processor and MBIST interface, track which locations are being tested, generate control signals for memory enable/disable, and coordinate test timing. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall complexity while enabling concurrent testing and operation.
Data Source
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AI summary
A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.